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RA4M1 数据表(PDF) 77 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 77 Page - Renesas Technology Corp |
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77 / 130 page  R01DS0355EJ0100 Rev.1.00 Page 77 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics Figure 2.52 SPI clock timing Figure 2.53 SPI timing for master when CPHA = 0 and the bit rate is set to any value other than PCLKA/2 RSPCKn master select output RSPCKn slave select input tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC n = A or B tDr, tDf tSU tH tLEAD tTD tLAG tSSLr, tSSLf tOH tOD M SB IN DATA LSB IN M SB IN M SB O UT DATA LSB O UT IDLE M SB O UT SSLn0 to SSLn3 output RSPCKn CPO L = 0 output RSPCKn CPO L = 1 output MISO n input MOSIn output n = A or B |
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