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RA4M1 数据表(PDF) 62 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 62 Page - Renesas Technology Corp |
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62 / 130 page  R01DS0355EJ0100 Rev.1.00 Page 62 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics 2.3.4 Wakeup Time Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Note 4. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h. Note 5. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h. Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.24 Timing of recovery from low power modes (1) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 tSBYMC -2 3 ms Figure 2.34 System clock source is PLL (48 MHz) with main clock oscillator*2 tSBYPC -2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz)*3 tSBYEX -14 25 μs System clock source is PLL (48 MHz) with main clock oscillator*3 tSBYPE -53 76 μs System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO -43 52 μs System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO -44 52 μs System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO -82 110 μs System clock source is MOCO tSBYMO -16 25 μs Table 2.25 Timing of recovery from low power modes (2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz)*2 tSBYMC -2 3 ms Figure 2.34 System clock source is PLL (24 MHz) with main clock oscillator*2 tSBYPC -2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz)*3 tSBYEX -2.9 10 μs System clock source is PLL (24 MHz) with main clock oscillator*3 tSBYPE -49 76 μs System clock source is HOCO (24 MHz) tSBYHO -38 50 μs System clock source is MOCO tSBYMO -3.5 5.5 μs |
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