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RA4M1 数据表(PDF) 71 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 71 Page - Renesas Technology Corp |
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71 / 130 page ![]() R01DS0355EJ0100 Rev.1.00 Page 71 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics Figure 2.46 SCI simple SPI mode clock timing Figure 2.47 SCI simple SPI mode timing for master when CKPH = 1 Simple SPI Slave access time tSA - 10 (PCLKA > 32 MHz), 6 (PCLKA ≤ 32 MHz) tPcyc Figure 2.49 and Figure 2.50 Slave output release time tREL - 10 (PCLKA > 32 MHz), 6 (PCLKA ≤ 32 MHz) tPcyc Table 2.34 SCI timing (2) (2 of 2) Parameter Symbol Min Max Unit Test conditions tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC (n = 0 to 2, 9) SCKn master select output SCKn slave select input tDr, tDf tSU tH tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SCKn CKPOL = 0 output SCKn CKPOL = 1 output MISOn input MOSIn output (n = 0 to 2, 9) |
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