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RA4M1 数据表(PDF) 44 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 44 Page - Renesas Technology Corp |
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44 / 130 page  R01DS0355EJ0100 Rev.1.00 Page 44 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics 2.2.9 Operating and Standby Current Table 2.11 Operating and standby current (1) (1 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Typ*10 Max Unit Test conditions Supply current *1 High-speed mode *2 Normal mode All peripheral clock disabled, while (1) code executing from flash *5 ICLK = 48 MHz ICC 8.3 - mA *7 ICLK = 32 MHz 5.8 - ICLK = 16 MHz 3.5 - ICLK = 8 MHz 2.2 - All peripheral clock disabled, CoreMark code executing from flash *5 ICLK = 48 MHz 16.4 - ICLK = 32 MHz 11.3 - ICLK = 16 MHz 6.4 - ICLK = 8 MHz 4.0 - All peripheral clock enabled, while (1) code executing from flash *5 ICLK = 48 MHz 18.5 - *9 ICLK = 32 MHz 13.8 - *8 ICLK = 16 MHz 7.7 - ICLK = 8 MHz 4.5 - All peripheral clock enabled, code executing from SRAM *5 ICLK = 48 MHz - 50.0 *9 Sleep mode All peripheral clock disabled *5 ICLK = 48 MHz 3.3 - *7 ICLK = 32 MHz 2.4 - ICLK = 16 MHz 1.8 - ICLK = 8 MHz 1.4 - All peripheral clock enabled *5 ICLK = 48 MHz 13.4 - *9 ICLK = 32 MHz 10.4 - *8 ICLK = 16 MHz 6.0 - ICLK = 8 MHz 3.6 - Increase during BGO operation *6 2.5 - - Middle-speed mode *2 Normal mode All peripheral clock disabled, while (1) code executing from flash *5 ICLK = 12 MHz ICC 2.5 - mA *7 ICLK = 8 MHz 2.0 - ICLK = 1 MHz 0.9 - All peripheral clock disabled, CoreMark code executing from flash *5 ICLK = 12 MHz 4.7 - ICLK = 8 MHz 3.7 - ICLK = 1 MHz 1.2 - All peripheral clock enabled, while (1) code executing from flash *5 ICLK = 12 MHz 5.7 - *8 ICLK = 8 MHz 4.3 - ICLK = 1 MHz 1.5 - All peripheral clock enabled, code executing from SRAM *5 ICLK = 12 MHz - 20.0 Sleep mode All peripheral clock disabled *5 ICLK = 12 MHz 1.2 - *7 ICLK = 8 MHz 1.2 - ICLK = 1 MHz 0.8 - All peripheral clock enabled *5 ICLK = 12 MHz 4.4 - *8 ICLK = 8 MHz 3.4 - ICLK = 1 MHz 1.4 - Increase during BGO operation *6 2.5 - - |
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