RA4M1 datasheet(56/130 Pages) RENESAS

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R01DS0355EJ0100 Rev.1.00

Page 56 of 130

Oct 8, 2019

RA4M1 Group

2. Electrical Characteristics

Note 1.

The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2.

The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3.

The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use.

Note 4.

See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 5.

The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Note 1.

The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory.

Note 2.

The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use.

Note 3.

See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 4.

The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Note 1.

The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2.

The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3.

The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-Bit A/D converter is in

use.

Note 4.

See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 5.

The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Table 2.19

Operation frequency value in Low-speed mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*4

Unit

Operation

frequency

System clock (ICLK)*3

1.8 to 5.5 V

0.032768

MHz

Flash interface clock (FCLK)*1, *3

1.8 to 5.5 V

0.032768

Peripheral module clock (PCLKA)*3

1.8 to 5.5 V

Peripheral module clock (PCLKB)*3

1.8 to 5.5 V

Peripheral module clock (PCLKC)*2, *3

1.8 to 5.5 V

Peripheral module clock (PCLKD)*3

1.8 to 5.5 V

Table 2.20

Operation frequency value in low-voltage mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*4

1.6 to 5.5 V

0.032768

MHz

Flash interface clock (FCLK)*1, *2, *4

1.6 to 5.5 V

0.032768

Peripheral module clock (PCLKA)*4

1.6 to 5.5 V

Peripheral module clock (PCLKB)*4

1.6 to 5.5 V

Peripheral module clock (PCLKC)*3, *4

1.6 to 5.5 V

Peripheral module clock (PCLKD)*4

1.6 to 5.5 V

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