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RA4M1 数据表(PDF) 82 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 82 Page - Renesas Technology Corp |
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82 / 130 page ![]() R01DS0355EJ0100 Rev.1.00 Page 82 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics 2.3.11 SSIE Timing Figure 2.60 SSIE clock input/output timing Table 2.38 SSIE timing Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Min Max Unit Test conditions SSIE AUDIO_CLK input frequency 2.7 V or above tAUDIO -25 MHz - 1.6 V or above - 4 Output clock period tO 250 - ns Figure 2.60 Input clock period tI 250 - ns Clock high pulse width 1.8 V or above tHC 100 - ns 1.6 V or above 200 - Clock low pulse width 1.8 V or above tLC 100 - ns 1.6 V or above 200 - Clock rise time tRC -25 ns Data delay 2.7 V or above tDTR -65 ns Figure 2.61, Figure 2.62 1.8 V or above - 105 1.6 V or above - 140 Set-up time 2.7 V or above tSR 65 - ns 1.8 V or above 90 - 1.6 V or above 140 - Hold time tHTR 40 - ns SSITXD0 output delay from SSILRCK0/SSIFS0 change time 1.8 V or above TDTRW - 105 ns Figure 2.63 1.6 V or above - 140 SSIBCK0 tHC tLC tRC tI, tO |
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