RA4M1 datasheet(45/130 Pages) RENESAS

45 / 130 page

R01DS0355EJ0100 Rev.1.00

Page 45 of 130

Oct 8, 2019

RA4M1 Group

2. Electrical Characteristics

Note 1.

Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

Note 2.

The clock source is HOCO.

Note 3.

The clock source is MOCO.

Note 4.

The clock source is the sub-clock oscillator.

Note 5.

This does not include BGO operation.

Note 6.

This is the increase for programming or erasure of the flash memory for data storage during program execution.

Note 7.

FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64.

Note 8.

FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same frequency as that of ICLK.

Note 9.

FCLK and PCLKB are set to divided by 2 and PCLKA, PCLKC, and PCLKD are the same frequency as that of ICLK.

Note 10. VCC = 3.3 V.

Supply

current

Low-speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 1 MHz

ICC

0.4

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 1 MHz

0.6

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 1 MHz

1.0

All peripheral clock

enabled, code executing

from SRAM

ICLK = 1 MHz

2.2

Sleep mode

All peripheral clock

disabled

ICLK = 1 MHz

0.3

All peripheral clock

enabled

ICLK = 1 MHz

0.9

Low-voltage

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 4 MHz

ICC

1.7

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 4 MHz

2.8

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 4 MHz

3.0

All peripheral clock

enabled, code executing

from SRAM

ICLK = 4 MHz

8.0

Sleep mode

All peripheral clock

disabled

ICLK = 4 MHz

1.3

All peripheral clock

enabled

ICLK = 4 MHz

2.5

Subosc-

speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 32.768 kHz

ICC

8.5

μA

All peripheral clock

enabled, while (1) code

executing from flash*5

ICLK = 32.768 kHz

14.9

All peripheral clock

enabled, code executing

from SRAM*5

ICLK = 32.768 kHz

83.0

Sleep mode

All peripheral clock

disabled

ICLK = 32.768 kHz

5.0

All peripheral clock

enabled

ICLK = 32.768 kHz

11.4

Table 2.11

Operating and standby current (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Typ*10

Max

Unit

Test

conditions

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