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RA4M1 数据表(PDF) 102 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 102 Page - Renesas Technology Corp |
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102 / 130 page ![]() R01DS0355EJ0100 Rev.1.00 Page 102 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics Figure 2.74 Power-on reset timing Figure 2.75 Voltage detection circuit timing (Vdet0) Note: tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the valid voltage (1.0 V). When VCC turns on, maintain tW(POR) for 1.0 ms or more. Internal reset signal (active-low) VCC tPOR VPOR 1.0 V tW(POR) *1 tdet tVOFF tLVD0 tdet Vdet0 VCC Internal reset signal (active-low) tdet VLVH |
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