EDBA164B4PR-1DATF-R datasheet(113/152 Pages) MICRON

113 / 152 page

2. For CK_t and CK_c, use VIH/VIL(AC) of CA and VREFCA; for DQS_t and DQS_c, use VIH/VIL(AC)

of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the re-

duced voltage level also applies.

3. Used to define a differential signal slew rate. For CK_t - CK_c use VIH/VIL(dc) of CA and

VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or

dc-low level is used for a signal group,then the reduced level applies also here.

Table 72: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC)

Slew Rate (V/ns)

tDVAC (ps) at VIH/VILdiff(AC) = 440mV

tDVAC (ps) at VIH/VILdiff(AC) = 600mV

Min

> 4.0

175

4.0

170

3.0

167

2.0

163

1.8

162

1.6

161

1.4

159

1.2

155

1.0

150

< 1.0

150

Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c, DQS_t, and DQS_c)

must also comply with certain requirements for single-ended signals.

CK_t and CK_c must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS_t, DQS_c

must meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid

transition.

The applicable AC levels for CA and DQ differ by speed bin.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

AC and DC Logic Input Measurement Levels for Differential

Signals

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

113

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDBA164B4PR-1DATF-R 数据表(PDF) 113 Page - Micron Technology

EDBA164B4PR-1DATF-R 数据表(HTML) 113 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载