ADA4254ACPZ-R7 datasheet(28/59 Pages) AD

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ADA4254

Data Sheet

Rev. B | Page 28 of 59

sourced from VDDH (see Figure 86). Only one of the sources

can be on at one time. The source can be selected via EX_

CURRENT_SEL.

EX_CURRENT_SEL[1:0]

EX_CURRENT[3:0]

IOUT_HV

IOUT_LV

VDDH

AVDD

Figure 86. Excitation Current Configuration

The excitation currents can be programmed to a value from

100 μA to 1.5 mA in increments of 100 μA. The current output

is controlled via EX_CURRENT.

EXTERNAL CLOCK SYNCHRONIZATION

The ADA4254 uses an internal 1 MHz master clock. The

master clock is used to derive the 125 kHz chopping clock used

by the internal amplifiers. Either clock can be brought out on

the GPIO4 pin to allow synchronization of external systems.

Use the following procedure to enable the external clock

synchronization feature:

Configure GPIO4 as an output by setting Bit 4 in the

GPIO_DIR register to 1.

Enable the internal oscillator output special function by

setting the INT_CLK_OUT bit to 1 and the EXT_CLK_

IN bit to 0 in the SF_CFG register.

To output the 125 kHz clock, set the CLK_OUT_SEL bit in

the SYNC_CFG register to 1. To output the 1 MHz clock,

set the CLK_OUT_SEL bit to 0.

The ADA4254 can alternatively be configured to accept an

external clock on GPIO4. The ADA4254 allows external clocks

ranging from 1 MHz up to 32 MHz. In the case of an external

clock that is higher than 1 MHz, the input clock must be divided

down to 1 MHz using the internal clock divider. The edge on

which the ADA4254 synchronizes can also be configured.

Use the following procedure to configure the ADA4254 to

accept an external clock on GPIO4:

Configure GPIO4 as an input by setting Bit 4 in the

GPIO_DIR register to 0.

Set the EXT_CLK_IN bit to 1 and ensure that the

INT_CLK_OUT bit is set to 0 in the SF_CFG register.

Depending on the frequency of the input clock, configure

the internal clock divider value such that the resulting clock is

1 MHz. The internal clock divider value is controlled by

the SYNC bits in the SYNC_CFG register.

For synchronizing on the rising edge, set the SYNC_POL bit

in the SYNC_CFG register to 1. For synchronizing on the

falling edge, set SYNC_POL to 0.

To maintain the performance of the ADA4254, the external

clock must in the specified range. The quality of the clock used

may affect the device performance. Prevent any overshoot or

undershoot on the clock used, and provide an equal rise and fall

to minimize the impact on the offset voltage.

SEQUENTIAL CHIP SELECT (SCS)

SCS is one of the special functions on the ADA4254 that can be

configured on the GPIO pins. This mode simplifies isolation

requirements by allowing multiple slave devices to communicate

over the SPI using a single host chip select (CS) line. This

communication also supports CRC checksums transparently.

A GPIO is configured for SCS by first setting the GPIO as an

output using a GPIO_DIR bit, and then setting the respective

bit in the SCS register. Configuring a GPIO for SCS mode is

blocked if the GPIO is already configured for another function

from the special functions register, SF_CFG.

When using SCS, the CS signal from the SPI host controller is

provided to the ADA4254 CS pin. The serial data input (SDI),

serial data output (SDO), and serial clock (SCLK) are shared

connections with other SPI devices. The ADA4254 SDO pin

supports tristate operation. Slave SDO pins can be directly

connected to SDO if the slave pins support tristate operation.

For slave devices with SDO pins that do not support tristate

operation, an OR gate can be used to combine the SDO signals.

If external logic is used to combine SDO lines, pull-down or

pull-up resistors are recommended to avoid floating logic gate

inputs. Figure 87 and Figure 88 show typical implementations. It

is recommended to place pull-up resistors on the GPIOs

configured in SCS mode to prevent any unintended

communication with slave devices when configuring the ADA4254

in SCS mode.

ADA4254ACPZ-R7 数据表(PDF) 28 Page - Analog Devices

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