ADA4254ACPZ-R7 datasheet(29/59 Pages) AD

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Data Sheet

ADA4254

Rev. B | Page 29 of 59

ADuCM4050

SCLK

MOSI

MISO

ADA4254

SCLK

SDI

SDO

GPIO/SCS

10kΩ

DIGITAL

SUPPLY

ADC

SCLK

SDI

SDO

DAC

SCLK

SDI

SDO

ADuM141E

ADuM141D

Figure 87. Typical SCS Implementation with Devices Without SDO Tristate Support

ADuCM4050

ADuM141E

ADuM141D

SCLK

MOSI

MISO

ADA4254

SCLK

SDI

SDO

GPIO/SCS

SCLK

SDI

SDO

SCLK

SDI

SDO

10kΩ

DIGITAL

SUPPLY

ADC

DAC

Figure 88. Typical SCS Implementation with All Devices Supporting SDO Tristate

When configured for SCS, communication with the ADA4254

and all slave devices follows a predefined pattern. The first CS

pulse is passed to the first GPIO that is set up for SCS,

effectively communicating with the first slave device.

Subsequent CS pulses progress through any GPIOs configured

for SCS in ascending order. The last CS pulse addresses the

ADA4254 itself. This pattern repeats until SCS is disabled.

Figure 87 and Figure 88 show the ADA4254 operating in SCS

mode with GPIO0 and GPIO1 communicating with two slave

devices. GPIO0 is connected to the CS line of an ADC. GPIO1

is connected to the CS line of a DAC.

In Figure 89, five distinct CS pulses can be seen. The first CS

pulse writes 0x03 to the GPIO_DIR register to configure

GPIO0 and GPIO1 as outputs. The second CS pulse writes 0x03

to SCS to configure GPIO0 and GPIO1 for SCS. The third CS

pulse is replicated on GPIO0 and communicates with the first

slave device, an ADC in this case. The fourth CS pulse is

replicated on GPIO1 and communicates with the second slave

device, a DAC in this case. The fifth CS pulse communicates

with the ADA4254 itself. This pattern of communication

continues in order of ADC, DAC, and ADA4254 until SCS is

changed.

GPIO0/SCS0

SCK

SDO

SDI

GPIO1/SCS1

M10.0µs

A CH1

340V

26.72000µs

Figure 89. SCS Configuration and Operation with Two Slave Devices

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