ADA4254ACPZ-R7 datasheet(8/59 Pages) AD

部件名	ADA4254ACPZ-R7

功能描述	Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier

PDF	59 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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8 / 59 page

ADA4254

Data Sheet

Rev. B | Page 8 of 59

TIMING SPECIFICATIONS

VDDH = 28 V, VSSH = −28 V, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, DVSS = 0 V, VOCM = AVDD/2 V.

Table 2. Digital Values and SPI Timing Specifications

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width (SCLK)

High

tPWH

Low

tPWL

SDI/SDO to SCLK Setup Time

tDS

SDI/SDO to SCLK Hold Time

tDH

Data Valid, SDO to SCLK

tDV

Setup Time, CS to SCLK

Timing Diagrams

R/W A6 A5A4 A3

A2 A1A0 D7N D6N D5N

D00

D10

D20

D30

D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

SDO

Figure 2. SPI Timing Diagram, MSB First

SCLK

SDI

INSTRUCTION BIT 6

INSTRUCTION BIT 7

tDCS

tDS

tDH

tPWH

tPWL

tSCLK

Figure 3. SPI Register Write Timing Diagram

SCLK

SDI,

SDO

DATA BITn–1

DATA BIT n

tDV

Figure 4. SPI Register Read Timing Diagram

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