ADA4254ACPZ-R7 datasheet(35/59 Pages) AD

35 / 59 page

Data Sheet

ADA4254

Rev. B | Page 35 of 59

CRC CALCULATION

The checksum, which is 8 bits wide, is generated using the

following polynomial (with a seed of 0x00):

x8 + x2 + x + 1 (0b100000111)

To generate the checksum, the data is left shifted by 8 bits to

create a number ending in eight Logic 0s. The polynomial is

aligned so that its MSB is adjacent to the leftmost Logic 1 of the

data. An exclusive OR (XOR) function is applied to the data to

produce a new, shorter number. The polynomial is again aligned

so that its MSB is adjacent to the leftmost Logic 1 of the new

result, and the procedure is repeated. This process is repeated

until the original data is reduced to a value less than the

polynomial. This is the 8-bit checksum.

100 001 10 011 000 000 000 000 0

100 000 11 1

000 001 01 1

SEED = 0x00

1 00 000 111

0 01 111 111

1 000 001 11

0 111 110 11

100 000 111

011 110 001

10 000 011 1

01 110 010 1

1 000 001 11

0 110 011 01

100 000 111

010 011 101

10 000 011 1

00 011 110 1

10 000 011 1

01 110 111 1

CRC CHECKSUM

Figure 98. Calculating a CRC Checksum

MEMORY MAP CHECKSUM PROTECTION

For added robustness, a CRC calculation is performed on the

on-chip registers as well. Register 0x03, Register 0x04, and

these registers change, independent of SPI writes. The CRC is

performed at a rate of 15.26 Hz. Each time the register map is

changed using an SPI write, the CRC is recalculated.

The memory map CRC function is enabled by default. It can

be disabled via MM_CRC_ERR_DIS. If an error occurs,

MM_CRC_ERR trips.

VERIFY DATA USING CRC CHECKSUM

100 0011 001 100 0001 110 111 1

100 0001 11

000 0010 11

CRC CHECKSUM = 0xEF

10 000 011 1

00 111 111 1

100 000 111

011 111 011

10 000 0111

01 111 0000

1 000 0011 1

0 111 0011 0

100 0001 11

011 0010 10

10 0000 111

01 0010 011

1 0000 011 1

0 0010 000 0

10 000 011 1

00 000 000 0

REMAINDER = 0

DATA OK!

Figure 99. Verifying Data with a CRC Checksum

READ-ONLY MEMORY (ROM) CHECKSUM

PROTECTION

On power-up, all fuse registers are set to the default values.

These default values are held in ROM. For added robustness, a

CRC calculation is performed on the ROM contents as well.

This CRC check is performed on power-up. The ROM CRC

function is enabled by default. It can be disabled via ROM_

CRC_ERR_DIS. If an error occurs, the ROM_CRC_ERR trips.

SPI READ/WRITE ERROR DETECTION

The ADA4254 can detect if an invalid register is being addressed.

A read or write to an invalid address trips SPI_RW_ERR.

SPI_RW_ERR is enabled by default. It can be disabled via

SPI_RW_ERR_DIS.

SPI COMMAND LENGTH ERROR DETECTION

When communicating with the ADA4254, the number of clock

edges on SCLK is monitored to ensure that, when CS returns

high, the total number of clock edges received is divisible by 8.

If the number of SCLK edges is insufficient or in excess, SPI_

SCLK_CNT_ERR trips. The SPI_SCLK_CNT_ERR is enabled

by default. It can be disabled via SPI_SCLK_CNT_ERR_DIS.

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