ADA4254ACPZ-R7 datasheet(31/59 Pages) AD

31 / 59 page

Data Sheet

ADA4254

Rev. B | Page 31 of 59

For all gains using 1 V/V scalar, calculate the gain error using

the following equation:

Gain Error = ((−1) × GAIN_CALx, Bit 4 + (100) ×

GAIN_CALx, Bits[3:0]) (ppm)

For all gain values using 1.375 V/V or 1.25 V/V scalars, an

additional gain error (GE’) must be added, using this equation:

GE’ = Gain Error + ((−1) × GAIN_CALx, Bit 4 + (50) ×

GAIN_CALx, Bits[3:0]) (ppm)

For example, assume that the ADA4254 is set to a gain of 32 V/V

and a scaling gain of 1.375 V/V. To calculate the stored gain

error, read the gain error stored in the GAIN_CAL10 register

and calculate the error in ppm. In this example, assume this

readback is 10101, corresponding to a gain error of −500 ppm.

Then, read the additional gain error stored in GAIN_CAL17

and calculate the error in ppm. In this example, assume this

readback is 00010, corresponding to an additional gain error of

100 ppm. The two errors are added to give a total gain error of

−400 ppm.

WIRE BREAK DETECTION

The ADA4254 contains two programmable current sources

that can be configured to 0.25 μA, 2 μA, 4 μA, or 16 μA via

WB_CURRENT. Both currents are conducted from VDDH.

These currents, in conjunction with the on-chip comparators,

enable continuity testing on the ADA4254 inputs.

The currents are switched to the amplifier inputs using F1 and

F2, as shown in Figure 90. The voltage to which these currents

bias the amplifier inputs is monitored internally by the

ADA4254. When this voltage is within 4 V of VDDH, the

WB_ERR flag trips.

When F1 or F2 are closed, the amplifier gain settings in the

GAIN_MUX register are temporarily overridden to the default

values to avoid saturating the amplifier output in the event of an

open circuit input. Reads of the GAIN_MUX register during

this time do not reflect this. When F1 and F2 are open, the

GAIN_MUX values automatically return to the previous values.

This override can be disabled via WB_G_RST_DIS.

VDDH

+IN1

–IN1

+IN2

–IN2

D12

–OUT

PGIA

+OUT

WB_CURRENT[1:0]

Figure 90. Wire Break Current Connectivity

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