ADA4254ACPZ-R7 datasheet(36/59 Pages) AD

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ADA4254

Data Sheet

Rev. B | Page 36 of 59

APPLICATIONS INFORMATION

INPUT AND OUTPUT OFFSET VOLTAGE AND

NOISE

The offset voltage of the ADA4254 has two main components:

the input offset voltage due to the input amplifiers and the output

offset due to the output amplifier. The total offset voltage RTI is

found by dividing the output offset by the programmed gain

and adding to the input offset voltage. At high gains the input

offset voltage dominates, whereas at low gains the output offset

voltage dominates. The total offset voltage is

Total Input Offset Voltage (RTI) =VOSI + (VOSO/GAIN)

Total Output Offset Voltage (Referred to Output (RTO)) =

VOSI × Gain + VOSO

The preceding equations can also be used to calculate the offset

drift in a similar manner.

The ADA4254 has extremely low input offset voltage long-term

drift, as shown in Figure 100. This high level of stability is due to

the zero drift architecture of the ADA4254 amplifiers. This

testing is performed at 25°C with the ADA4254 devices

submerged in an oil bath.

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

500

1500

2000

2500

3000

3500

4000

4500

1000

TIME (Hours)

N = 20 UNITS

NORMALIZED AT HOUR 0

Figure 100. Input Offset Voltage Long-Term Drift

The noise of the ADA4254 behaves similarly to the voltage

offset. There are two components: the input voltage noise due

to the input amplifiers and the output voltage noise due to the

output amplifiers. The total noise RTI is found by dividing the

output voltage noise by the programmed gain and root-sum-

squaring with the input voltage noise. At high gains the input

voltage noise dominates, whereas at low gains the output

voltage noise dominates. The total voltage noise is

Total Input Voltage Noise (RTI) =

Gain



 



Total Output Voltage Noise (RTO) =

()

(

)

eGain



ADC CLOCK SYNCHRONIZATION

The ADA4254 incorporates several clock synchronization

features that allow the internal clock to be synchronized with

other circuitry, such as an ADC. Synchronizing the system

filters residual ripple due to the internal chopping of the

ADA4254. When using these synchronization features, GPIO4

is configured to accept an external clock signal or output one of

the internal clock signals.

When an external clock is provided to the AD4254, an on-chip

clock divider is configured via SYNC to achieve a nominal 1 MHz

clock. The 1 MHz clock is further divided by 8 to 125 kHz and

controls the device chopping. The chopping clock edges can be

configured to coincide with either the rising or falling edges of

the provided clock via SYNC_POL. This configuration is

recommended for ADC synchronization.

Alternatively, the internal clock can be output to GPIO4 so that

other circuits can use it. Either 1 MHz or 125 kHz can be

selected via CLK_OUT_SEL.

When ADA4254 is driving the AD4007 1 MSPS successive

approximation register (SAR) ADC as shown in Figure 101, the

recommended configuration is to provide the convert signal to

the ADA4254 as a clock input. In this case, SYNC is set to 0b000

because the CNV period is 1 μs. Set SYNC_POL to 1 to synchro-

nize the chopping clock to the rising edge of the CNV signal.

When configured in this way, the output of the ADA4254 has

the maximum time to settle after a chopping edge and

chopping edges do not occur during the ADC conversion

phase. It is recommended to enable the high-Z mode of the

AD4007 to maximize system performance.

When the ADA4254 is driving the AD7768 Σ-Δ ADC as shown

in Figure 102, the recommended configuration is to provide the

internal 32 MHz clock of the AD7768 to the ADA4254 as a clock

input. In this case, SYNC is set to 0b101 to divide 32 MHz

down to 1 MHz for the ADA4254. The SYNC setting has no

impact on performance with Σ-Δ converters due to the way the

converters operate internally. When driving the AD7768

directly with the ADA4254, enable the internal buffers of the

AD7768. Alternatively, a dedicated ADC driver/amplifier can be

configured between the ADA4254 and the AD7768.

In both configurations, it is recommended that two reads from

the M_CLK_CNT register are performed to ensure that the

master clock counter is incrementing, indicating that the

ADA4254 is receiving an external clock.

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