ADA4254ACPZ-R7 datasheet(33/59 Pages) AD

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Data Sheet

ADA4254

Rev. B | Page 33 of 59

DIGITAL INTERFACE

SPI INTERFACE

The ADA4254 features a 4-wire SPI interface. This interface

operates in SPI Mode 0 and can be operated with CS tied low.

In SPI Mode 0, SCLK idles low, the falling edge of SCLK is the

driving edge, and the rising edge of SCLK is the sampling edge.

This setup means that data is clocked out on the falling (driving)

edge and data is clocked in on the rising (sampling) edge.

DRIVE EDGE

SAMPLE EDGE

Figure 93. SPI Mode 0 SCLK Edges

ACCESSING THE ADA4254 REGISTER MAP

The ADA4254 SPI interface uses 16-bit instructions, plus an

optional 8-bit CRC checksum. Each instruction contains a

read/write bit, a 7-bit address, 8 bits of data, and an 8-bit CRC

checksum if the SPI_CRC_ERR bit is configured.

Table 8. ADA4254 Instruction Format

ADDR[6:0]

DATA[7:0]

CRC[7:0]

RW determines whether a read or write operation is performed

(1 means read and 0 means write). ADDR[6:0] is the register

address being read from or written to. RW and the ADDR[6:0]

together are referred to as an 8-bit command. For write operations,

DATA[7:0] is the data being written and CRC[7:0] is a user

provided checksum for that data.

The ADA4254 internal address counter is automatically

incremented after each read/write operation, allowing a

continuous read/write mode. After an initial read operation, if

CS stays low, the next 8 SCLK pulses read back the contents of

the next register address. After an initial write operation, if CS

stays low, the next 8 SCLK pulses load the data on SDI to the

next register address.

CHECKSUM PROTECTION

The ADA4254 features a checksum mode that can be used to

improve interface robustness. Using the checksum ensures that

only valid data is written to a register and allows data read from

a register to be validated. If an error occurs during a register

write, SPI_CRC_ERR trips and no data is written. To ensure

that a register write is successful, the register contents can be

read, and the checksum can be verified.

For CRC checksum calculations, the following polynomial is

always used:

x8 + x2 + x + 1

SPI_CRC_ERR_DIS enables and disables this checksum. The 8-bit

checksum is appended to the end of each read and write trans-

action. The checksum calculation for the write transaction is

calculated using the 8-bit command word and the 8-bit data.

For a read transaction, the checksum is calculated using the

command word and the 8-bit data output. Figure 94 and Figure 95

show SPI write and read transactions, respectively.

In continuous write mode, the first write command CRC is

calculated as described previously in this section. Subsequent CRCs

are clocked in after every register data. CRC in continuous write

mode is calculated based on the register value it is associated

with. In continuous read mode, the first read command CRC is

calculated as described previously. Subsequent CRCs are clocked

out after every register data. CRC in continuous read mode is

calculated based only on the register value it is associated with.

Figure 96 and Figure 97 show SPI continuous write and read

transactions, respectively.

8-BIT COMMAND

DATA

CRC

8-BIT INPUT

8-BIT CRC

SDI

SCLK

Figure 94. Writing to a Register with CRC

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