ADA4254ACPZ-R7 datasheet(39/59 Pages) AD

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Data Sheet

ADA4254

Rev. B | Page 39 of 59

AD7768

AVDD/2

OUT–

ADA4254

OUT+

AVSS

GPIO4/CLKIN

10kΩ

MCLK

200Ω

680pF

200Ω

270pF

–

+IN1

–IN1

+IN2

–IN2

AVDD1

VOCM

AVSS

AIN0+

AIN0–

AVDD

VSSH

VDDH

–15V

RL1

RL2

RTD

RL3

RREF

IOUT_LV

IOUT_HV

+15V

Figure 104. 3-Wire RTD Application

AD4007

AVDD/2

OUT–

ADA4254

OUT+

AVSS

GPIO4/CLKIN

10kΩ

CNV

200Ω

500pF

–

+IN1

–IN1

+IN2

–IN2

VDD

VOCM

GND

IN+

IN–

AVDD

VSSH

VDDH

+28V

–28V

RFILTER

CFILTER

RSHUNT

HIGH SIDE

SUPPLY

LOAD

ADP7112-1.8V

OUT

Figure 105. Current Sense Application

HIGH RAIL CURRENT SENSING

In high side configuration (current sensing configuration), the

shunt resistor is referenced to the high supply side. High voltage

is present at the inputs of the ADA4254. With the high common-

mode voltage range, the ADA4254 multiplexer can withstand

up to ±25 V on a ±28 V supply. The ADA4254 is ideal for

measuring currents with a wide dynamic range because of the

featured gain values, ranging from attenuation gains as low as

1/16 V/V to high gains up to 176 V/V with excellent gain

linearity and low offset voltage over temperature.

A low-pass filter minimizes the noise coupling in the measure-

ments. The ADA4254 has very low input bias current and input

bias offset current, which minimizes the error introduced by

the input bias current flowing through the resistor filter. The

matching of the filter resistors is required to minimize the error

contribution. The filter capacitors matching is also important.

Any mismatch in the capacitor value results in a degradation in

the CMMR of the ADA4254.

The ADA4254 internal chopping circuitry can be synchronized

to the companion ADC. This keeps the residual chopping noise

at the correct frequency and prevents it from folding back to a

frequency band of interest. To use the synchronization

functionality, configure GPIO4 to be an input by setting the

corresponding bit field in the GPIO_DIR register. Set the ADA4254

to accept an external clock by setting the EXT_CLK_IN bit field in

the SF_CFG register. Adjust the clock divider such that the

resulting clock is equal to 1 MHz. The divider can be adjusted

in SYNC_CFG register. The SYNC_CFG register also controls

the syncing edge polarity. It is recommended that two reads

from the M_CLK_CNT register are performed to ensure that

the master clock counter is incrementing, indicating that the

ADA4254 is receiving an external clock.

The ADA4254 on-chip diagnostics allow the user to check the

circuit connections. In current sensing applications, the circuit

connections are verified using the wire break detection capabilities

of the ADA4254. The WB_DETECT flag is set if one of the

connections to the shunt resistors is missing. Finally, the CRC

check, SCLK counter, and SPI read/write check make the interface

more robust because any read/write operations that are not

valid are detected. The CRC check highlights if any bits are

corrupted when being transmitted between the processor and the

ADA4254.

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ADA4254ACPZ-R7 数据表(PDF) 39 Page - Analog Devices

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