ADA4254ACPZ-R7 datasheet(55/59 Pages) AD

55 / 59 page

Data Sheet

ADA4254

Rev. B | Page 55 of 59

TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS

Table 29. TEST_MUX Register Details (Register 0x0E)

Bit Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CAL_SEL

CAL_EN[1:0]

TEST_MUX[3:0]

Access

Reset

+IN1

–IN1

+IN2

–IN2

D12

–OUT

PGIA

+OUT

TEST MULTIPLEXER

TEST_MUX[3:0]

AVSS

DVSS

+20mV –20mV

Figure 109. Test Multiplexer Connectivity

Bit 7, G5—Output Amplifier Scaling Gain = 1

.25 V/V

Clearing Bit G4 to 0 and setting Bit G5 to 1 configures the output

amplifier to a scaling gain value of 1.25 V/V. This setting scales

the input amplifier gain configured in the GAIN_MUX register

by 1.25 V/V.

Table 30. Output Amplifier Scaling Gain Settings

Output Amplifier Scaling Gain (V/V)

1.375

1.25

Bit 6, CAL_SEL—Calibration Type Configuration

Clearing the CAL_SEL bit to 0 configures the ADA4254 to

perform quick calibrations. Setting CAL_SEL to 1 configures

the ADA4254 to perform full calibrations.

Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable

and Interval

CAL_EN enables scheduled calibrations and configures the

interval on which these calibrations execute. While calibrations

are executing, the inputs of the PGIA are not connected to the

input pins. The CAL_BUSY signal indicates when a calibration

is executing. CAL_BUSY can be output to GPIO2 by configuring

GPIO2 as an output via GPIO_DIR and setting CAL_BUSY_OUT

to 1. Minimize and avoid noise and input transients during

calibrations.

Table 31. Scheduled Calibration Configurations

CAL_EN, Bit 1

CAL_EN, Bit 0

Scheduled Calibration

Configuration

Disabled

Enabled, 33 sec interval

Enabled, 132 sec interval

Enabled, 495 sec interval

Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer

Configuration

The TEST_MUX[3:0] bits are used to configure the input test

multiplexers, which can switch four different signals to either of

the inputs for diagnostic and calibration purposes. These potentials

are AVSS, DVSS, +20 mV, and −20 mV. SW_C1 and SW_C2

must also be set to 1 for the outputs of these multiplexers to be

connected to the amplifier inputs.

Table 32. Test Multiplexer Configurations

TEST_MUX[3:0]

Noninverting Input

Inverting Input

0000

AVSS

0001

DVSS

AVSS

0100

AVSS

DVSS

0101

DVSS

1010

+20 mV

1111

−20 mV

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ADA4254ACPZ-R7 数据表(PDF) 55 Page - Analog Devices

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