ADA4254ACPZ-R7 datasheet(38/59 Pages) AD

38 / 59 page

ADA4254

Data Sheet

Rev. B | Page 38 of 59

AVDD/2

OUT–

ADA4254

OUT+

AVSS

GPIO4/CLKIN

10kΩ

200Ω

680pF

200Ω

270pF

RFILTER

CFILTER

100Ω

10ppm/°C

150Ω

30V

±10V AND

4mA TO 20mA

RFILTER

GPIO0

–

+IN1

–IN1

+IN2

–IN2

VOCM

AVDD

VSSH

VDDH

–15V

AD7768

MCLK

AVDD1

AVSS

AIN0+

AIN0–

Figure 103. Voltage/Current Input Application

3-WIRE RTD WITH CURRENT EXCITATION

For a 3-wire RTD configuration, as shown in Figure 104, one

current source is needed to perform the measurement. In this

example circuit, IOUT_LV is used. The excitation current flows

through RL1, RTD, and RL3 reference resistor (RREF). Assuming

that RL1, RL2, and RL3 are equal, the error voltages due to all

the leads are equal. The voltage between +IN1 and –IN1 measures

the voltage drop due to RL1 and the RTD. The voltage between

+IN1 and –IN2 can be used to calculate the lead resistor. The

second channel, +IN2 and –IN2, has a precision reference resistor

used to measure the absolute value of the current flowing from

IOUT_LV. A typical procedure for reading the RTD current is

as follows:

Run a calibration to null any offset voltage error in the

system by shorting the input of the instrumentational

amplifier to ground.

Set the ADA4254 input multiplexer to Channel 1, +IN1

and –IN1, by writing 0x60 to the INPUT_MUX register.

Switch IOUT_LV on by writing 0x40 to the EX_CURRENT_

CFG register. Also, set the current by writing to the

EX_CURRENT[3:0] bits.

Set the gain of the ADA4254 to the appropriate gain via

the GAIN_MUX register.

Take a reading on the ADC. This reading shows the

voltage drop across RL1, the RTD element.

Switch the ADA4254 input mux to Channel 2, +IN2 and

−IN2, by writing 0x18 to the INPUT_MUX register.

Take a reading on the ADC. This reading is the voltage

drop across RREF. IOUT_LV can be calculated from this

reading.

Measure between –IN1 and +IN2. First the input

multiplexer protection is disabled by setting the

MUX_PROT_DIS bit to allow a –IN1 and +IN2

configuration.

Set the INPUT_MUX register to 0x30.

10. Repeat Step 4.

11. Take a reading on the ADC. This reading is the voltage

drop across RL3 and RREF.

Use the measurement from Step 11, the absolute value of

IOUT_LV, and the RREF value to calculate the lead resistance.

The lead resistance is subtracted from the measurement in

Step 5 to calculate the voltage drop across the RTD element.

After the RTD voltage is calculated, the RTD resistance can be

calculated.

The ADA4254 internal chopping circuitry can be synchronized

to the companion ADC. This helps keep the residual chopping

noise at its frequency and prevents it from folding back into a

frequency band of interest. To use the sync functionality,

configure GPIO4 to be an input by setting its corresponding bit

field in the GPIO_DIR register. Set the ADA4254 to accept an

external clock by setting the EXT_CLK_IN bit field in the SF_CFG

equal to 1 MHz. The divider can be adjusted in SYNC_CFG

edge polarity. It is recommended that two reads from the

M_CLK_CNT register are performed to ensure that the master

clock counter is incrementing indicating that the ADA4254 is

getting an external clock.

The ADA4254 on-chip diagnostics allow the user to check the

circuit connections. In RTD applications, the circuit connections

are verified using the wire break detection capabilities of the

ADA4254. The WB_DETECT flag is set if one of the RTD wires

is missing. Finally, the CRC check, SCLK counter, and SPI

read/write check make the interface more robust because any

read/write operations that are not valid are detected. The CRC

check highlights if any bits are corrupted when being

transmitted between the processor and the ADA4254.

ADA4254ACPZ-R7 数据表(PDF) 38 Page - Analog Devices

ADA4254ACPZ-R7 数据表(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

数据表下载