ADA4254ACPZ-R7 datasheet(37/59 Pages) AD

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Data Sheet

ADA4254

Rev. B | Page 37 of 59

AD4007

AVDD/2

OUT–

ADA4254

OUT+

AVSS

GPIO4/CLKIN

10kΩ

CNV

200Ω

500pF

–

+IN1

–IN1

+IN2

–IN2

VDD

VOCM

GND

IN+

IN–

AVDD

VSSH

VDDH

ADP7112-1.8V

OUT

Figure 101. Clock Synchronization with the AD4007

AVDD/2

OUT–

ADA4254

OUT+

AVSS

GPIO4/CLKIN

10kΩ

200Ω

270pF

680pF

–

+IN1

–IN1

+IN2

–IN2

VOCM

AVDD

VSSH

VDDH

AD7768

MCLK

AVDD1

AVSS

AIN0+

AIN0–

Figure 102. Clock Synchronization with the AD7768

PROGRAMMABLE LOGIC CONTROLLER (PLC)

VOLTAGE/CURRENT INPUT

The circuit in Figure 103 shows the ADA4254 used to convert

typical PLC input signal ranges (±10 V, ±5 V, or 20 mA) to an

output voltage from 0 V to 5 V, compatible with high precision

ADCs, such as the AD7768. To perform a voltage measurement,

the ADA4254 input multiplexer is configured to Channel 1,

+IN1 and –IN1, by writing 0x60 to the INPUT_MUX register.

The MOSFET switch must be turned off by setting GPIO0 to

logic level low. GPIO0 must be configured as an output by

setting the corresponding bit field to 1 in the GPIO_DIR register.

The state of GPIO0 is controlled by the corresponding bit field

in the GPIO_DATA register. The ADA4254 gain can be

configured through the GAIN_MUX register, depending on the

input voltage level.

To perform a current measurement, the circuit shown in

Figure 103 provides two different shunt resistors, 250 Ω and

100 Ω. To select a 250 Ω resistor, the MOSFET switch must be

switched on by setting GPIO0 to logic level high using the

GPIO_DATA register. The measurement is performed using

Channel 1 of the ADA4254. To select 100 Ω, the MOSFET must be

turned off by setting GPIO0 to logic level low. Channel 2 must be

selected in this mode by writing 0x18 to the INPUT_MUX

The ADA4254 internal chopping circuitry can be synchronized

to the companion ADC. This keeps the residual chopping noise

at the correct frequency and prevents it from folding back

to a frequency band of interest. To use the synchronization

functionality, configure GPIO4 to be an input by setting the

corresponding bit field in the GPIO_DIR register. Set the ADA4254

to accept an external clock by setting the EXT_CLK_IN bit field

in the SF_CFG register. Adjust the clock divider such that the

resulting clock is equal to 1 MHz. The divider can be adjusted in

the SYNC_CFG register. The SYNC_CFG register also controls

the synchronizing edge polarity. It is recommended that two

reads from the M_CLK_CNT register are performed to ensure

that the master clock counter is incrementing, indicating that

the ADA4254 is receiving an external clock.

The ADA4254 on-chip diagnostics allow the user to check the

circuit connections. In PLC applications, the circuit connections

are verified using the wire break detection capabilities of the

ADA4254. The WB_DETECT flag is set if one of the input

connections is missing. Finally, the CRC check, SCLK counter,

and SPI read/write check make the interface more robust as any

read/write operations that is not valid is detected. The CRC

check highlights if any bits are corrupted when being

transmitted between the processor and the ADA4254.

ADA4254ACPZ-R7 数据表(PDF) 37 Page - Analog Devices

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ADA4254ACPZ-R7 数据表(PDF) 37 Page - Analog Devices

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