ADA4254ACPZ-R7 datasheet(32/59 Pages) AD

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ADA4254

Data Sheet

Rev. B | Page 32 of 59

TEST MULTIPLEXER

The ADA4254 contains an internal test multiplexer, as shown in

Figure 91, that connects the inputs of the ADA4254 to useful

voltages. To use the test multiplexer, the C1 and C2 switches

must be closed. These switches are controlled using the

INPUT_MUX register. It is recommended that the input

multiplexer be disconnected from any external inputs by

opening the A1, A2, B1, and B2 switches.

The TEST_MUX bits in the TEST_MUX register control the

test multiplexer. The test multiplexer can be configured in three

different states, as follows:



In the default state, the test multiplexer connects the

ADA4254 inputs to AVSS. This configuration can be used

during a full system calibration to null out errors, such as

offset voltage.



The test multiplexer can connect the noninverting input to

DVSS and the inverting input to AVSS, or vice versa. This

configuration can be used to detect any voltage difference

between AVSS and DVSS, which indicates poor connection.



The test multiplexer can also provide a 20 mV or −20 mV

differential signal to the inputs of the ADA4254. This

configuration can be used to verify the gain setting of the

ADA4254 and the PGIA functionality without applying an

external signal.

EXTERNAL MUX CONTROL

The ADA4254 is able to configure GPIO0 and GPIO1 to

control an external multiplexer. Writes to the EXT_MUX bits

in the GAIN_MUX register set the state of GPIO0 and GPIO1,

which in turn controls an external multiplexer. This setup allows

amplifier gain and external multiplexer settings to be configured

with a single SPI write, avoiding overload conditions. The external

mux special function can be configured via EXT_MUX_EN and

setting GPIO0 and GPIO1 to outputs, as shown in

Figure 92.

+IN1

–IN1

+IN2

–IN2

D12

–OUT

PGIA

+OUT

TEST MULTIPLEXER

TEST_MUX[3:0]

AVSS

DVSS

+20mV –20mV

Figure 91. Text Multiplexer Connectivity

+22V

–22V

+5V

VDDH

S0A

S0B

S1A

ADG5409

S4A

S1B

S4B

VSSH

AVDD

ADA4254

AVSS

GPIO2 GPIO1 GPIO0 DVDD

+3.3V

DVSS

RFILTER

DB RFILTER

+22V

–22V

VDD

1 OF 4

DECODER

A0 A1 EN

VSS

RFILTER

CFILTER

+IN1

–IN1

–IN2

+IN2

Figure 92. External Multiplexer Control Example

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