ADA4254ACPZ-R7 datasheet(53/59 Pages) AD

53 / 59 page

Data Sheet

ADA4254

Rev. B | Page 53 of 59

SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS

Table 26. SF_CFG Register Details (Register 0x0C)

Bit Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

INT_CLK_OUT

EXT_CLK_IN

FAULT_INT_OUT CAL_BUSY_OUT

EXT_MUX[1:0]

Access

Reserved

Reset

Reserved

Bit 5, INT_CLK_OUT—Internal Oscillator Output

When GPIO4 is configured as an output via GPIO_DIR and

INT_CLK_OUT is set to 1, one of the internal clocks is output

to GPIO4. CLK_OUT_SEL in the SYNC_CFG register

determines which internal clock is on GPIO4.

Bit 4, EXT_CLK_IN—External Oscillator Input

When GPIO4 is configured as an input via GPIO_DIR and

EXT_CLK_IN is set to 1, an external clock can be provided via

GPIO4. If this clock frequency is not 1 MHz, the on-chip clock

divider must be used to divide the clock via the SYNC[2:0] bits.

The default setting for the internal clock divider is 16.

Bit 3, FAULT_INT_OUT—Fault Interrupt Output

When GPIO3 is configured as an output via GPIO_DIR and

FAULT_INT_OUT is set to 1, the value in FAULT_INT

appears on GPIO3.

Bit 2, CAL_BUSY_OUT—Calibration Busy Output

When GPIO2 is configured as an output via GPIO_DIR and

CAL_BUSY_OUT is set to 1, the value in CAL_BUSY appears

on GPIO2.

Bits[1:0], EXT_MUX_EN[1:0]—Enable External

Multiplexer Control

Each bit in the EXT_MUX_EN[1:0] bit range enables GPIO1

and/or GPIO0 to be controlled via EXT_MUX in the

GAIN_MUX register.

ADA4254ACPZ-R7 数据表(PDF) 53 Page - Analog Devices

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ADA4254ACPZ-R7 数据表(PDF) 53 Page - Analog Devices

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