ST7LUS5 datasheet(103/124 Pages) STMICROELECTRONICS

103 / 124 page

ST7LUS5, ST7LU05, ST7LU09

Electrical characteristics

103/124

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

●

DLU: Electrostatic discharges (one positive then one negative test) are applied to each

pin of three samples when the micro is running to assess the latch-up performance in

dynamic mode. Power supplies are set to the typical values, the oscillator is connected

as near as possible to the pins of the micro and the component is put in reset mode.

This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,

refer to the application note AN1181.

12.8

I/O port pin characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 78.

Electrical sensitivities

Symbol

Parameter

Conditions

Class(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, meaning that when a device belongs to Class A it exceeds the JEDEC standard. B

Class strictly covers all the JEDEC criteria (international standard).

Static latch-up class

TA = +125°C

DLU

Dynamic latch-up class

VDD = 5.5V, fOSC = 4 MHz, TA = +25°C

Table 79.

General characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

-40°C to 125°C

0.3VDD

VIH

Input high level voltage

0.7VDD

Vhys

Schmitt trigger voltage

hysteresis(1)

Data based on characterization results, not tested in production

400

Input leakage current

VSS < VIN < VDD

±1

µA

Static current consumption

induced by each floating

input pin(2)

Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of

the I/O for example or an external pull-up or pull-down resistor (see Figure 48). Static peak current value

taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in

production. This value depends on VDD and temperature values.

Floating input mode

400

RPU

Weak pull-up equivalent

resistor(3)(4)

VIN =VSS

VDD = 5V

120

170

Ω

VDD = 3.3V

200(1)

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall

time(1)

CL = 50 pF

Between 10% and 90%

tr(IO)out

Output low to high level rise

time(1)

tw(IT)in

External interrupt pulse

time(5)

1tCPU

ST7LUS5 数据表(PDF) 103 Page - STMicroelectronics

ST7LUS5 数据表(HTML) 103 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载