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CS5320 数据表(PDF) 22 Page - Applied Micro Circuits Corporation |
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CS5320 数据表(HTML) 22 Page - Applied Micro Circuits Corporation |
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22 / 160 page  S5320 – PCI Match Maker: Signal Description 22 DS1656 AMCC Confidential and Proprietary Revision 5.03 – June 14, 2006 Data Sheet Table 2. PCI Bus System Signals Signal Type Description PCLK in PCI Clock. The rising edge of this signal is the reference upon which all other signals are based except for RST# and INTA#. The maximum PCLK frequency for the S5320 is 33 MHz and the minimum is DC (0 Hz). RST# in Reset brings the S5320 to a known state: - All PCI bus output signals tri-stated. - All open drain signals (i.e., SERR#) floated. - All registers set to their factory defaults. - Pass-Thru is returned to an idle state. - All FIFOs emptied. Table 3. PCI Bus Data Transfer Control Signals Signal Type Description FRAME# in Frame. This signal is driven by the current bus master to indicate the beginning and duration of a bus transaction. When FRAME# is first asserted, it indicates a bus transaction is beginning with a valid addresses and bus command present on AD[31:0] and C/BE[3:0]. Data transfers continue while FRAME# is asserted. FRAME# de-assertion indicates the transaction is in a final data phase or has completed. IRDY# in Initiator Ready. This signal is always driven by the bus master to indicate its ability to complete the cur- rent data phase. During write transactions, it indicates AD[31:0] contains valid data. TRDY# s/t/s Target Ready. This signal is driven by the selected target to indicate the target is able to complete the current data phase. During read transactions, it indicates AD[31:0] contains valid data. Wait states occur until both TRDY# and IRDY# are asserted together. STOP# s/t/s Stop. The Stop signal is driven by a selected target and conveys a request to the bus master to stop the current transaction. LOCK# in Lock. The lock signal provides for the exclusive use of a resource. The S5320 may be locked by one master at a time. IDSEL in Initialization Device Select. This pin is used as a chip select during configuration read or write transac- tions. DEVSEL# s/t/s Device Select. This signal is driven by a target decoding and recognizing its bus address. This signal informs a bus master whether an agent has decoded a current bus cycle. INTA# o/d Interrupt A. This signal is defined as optional and level sensitive. Driving it low will interrupt to the host. The INTA# interrupt is to be used for any single function device requiring an interrupt capability. Table 4. PCI Bus Error Reporting Signals Signal Type Description PERR# s/t/s Parity Error. Only for reporting data parity errors for all bus transactions except for Special Cycles. It is driven by the agent receiving data two clock cycles after the parity was detected as an error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. SERR# o/d System Error. Used to report address and data parity errors on Special Cycle commands and any other error condition having a catastrophic system impact. Special Cycle commands are not supported by the S5320. |
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