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S5320 – PCI Match Maker: PCI Configuration Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Built-In Self-Test Register (BIST)

The Built-In Self-Test (BIST) Register permits the

implementation of custom, user-specific diagnostics.

This register has four fields shown in Figure 15. Bit 7

defines S5320's support of a built-in self test. When bit

7 is set, writing a 1 to bit 6 produce an interrupt signal

on the Add-On bus. Bit 6 remains set until cleared by a

write operation to this register from the Add-On bus

interface. When bit 6 is reset, it is interpreted as com-

pletion of the self-test and an error is indicated by a

non-zero value for the completion code (bits 3:0).

Figure 15. Built-In Self-Test Register

Built-in Self-Test Address Offset 0Fh

Power-up value:

00h

Boot-load:

External nvRAM/EPROM offset

04Fh

Attribute:

D7, D5-0 Read Only, D6 as PCI bus

write only

Size:

8 bits

Bit

Description

BIST Capable. This bit indicates the Add-On device supports a built-in self-test when a 1 is returned. A 0 should

be returned if this self-test feature is not required. This field is read only from the PCI interface.

Start BIST. Writing a 1 to this bit indicates that the self-test should start. This bit can only be written if bit 7 is one.

When bit 6 is set, an interrupt is issued to the Add-On interface. Other than through a reset, Bit 6 can only be

cleared by a write to this element from the Add-On bus interface. The PCI bus specification requires that this bit

be cleared within 2 seconds after being set, or the device will be failed. This bit is read/write set (R/WS).

5:4

Reserved. These bits are reserved and are hardwired to 0.

3:0

Completion Code. This field provides a method for detailing a device-specific error. It is considered valid when

the start BIST (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful com-

pletion.

Completion Code (RO)

Reserved (RO)

Start BIST (R/WS)

BIST Capable (RO)

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