CS5320 datasheet(76/160 Pages) AMCC

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S5320 – PCI Match Maker: Operation Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Table 36. Reset General Control/Status Register

Bit

Description

31:29

nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory.

Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23

through 16. The sequence requires that the low-order address, high-order address, and then a data byte are

loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory.

D31 must be set to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become

0 (ready).

D31

D30

D29

W/R

Inactive

Load low address byte

Load high address

Begin write

Begin read

Ready

Busy

Cautionary note: The non-volatile memory interface is also available for access by the Add-On interface. While

simultaneous accesses to the nv memory by both the Add-On and PCI are supported, via arbitration logic, soft-

ware must be designed to prevent the possibility of data corruption within the memory and to provide for accu-

rate data retrieval.

nvRAM Access Failed. It will indicate that the last nvRAM access has failed. This flag is cleared automatically

upon the start of the next read/write operation.

Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not

necessary to write this bit to 0 afterwards because it is used internally to produce a reset pulse. Since reading

this bit will always return a 0, this bit is write only.

Reserved. Always zero.

Read FIFO Reset. Writing a one to this bit causes the read FIFO to reset (empty). It is not necessary to write a 0

to this bit. This bit is write only. This feature is intended for test only. It can only be asserted when the PCI is not

performing any Pass-Thru accesses.

Reserved. Always zero.

23:16

Non-volatile Memory Address/Data Port. This 8-bit field is used in conjunction with bits 31, 30 and 29 of this reg-

ister to access the external non-volatile memory. The contents written are either low address, high address, or

data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the

proper read sequence for bits 31 through 29 is performed.

15:12

BIST Condition Code. This field is directly connected to the PCI configuration self-test register. Bit 15 through 12

maps with the BIST register bits 3 through 0, respectively.

11:0

Reserved. Always zero.

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