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CS5320 数据表(PDF) 45 Page - Applied Micro Circuits Corporation |
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CS5320 数据表(HTML) 45 Page - Applied Micro Circuits Corporation |
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45 / 160 page ![]() S5320 – PCI Match Maker: PCI Configuration Registers Revision 5.03 – June 14, 2006 AMCC Confidential and Proprietary DS1656 45 Data Sheet Base Address Register (BADR) Base address registers are used by the system BIOS to determine how much memory or I/O address space a region requires in host space. The actual memory or I/O location(s) of the space is determined by interro- ga tin g th ese re gister s af ter BIOS po we r-u p initialization. Bit zero of each field is used to select whether the space required is to be decoded as mem- ory (bit 0 = 0) or I/O (bit 0 = 1). Since this PCI device has internal operating registers, the Base Address Register at offset 10h is assigned to them. The remaining four base address registers can only be used by boot-loading them from the external nvRAM interface. Determining Base Address Size The address space defined by a given base address register is determined by writing all 1s to a given base address register from the PCI bus and then reading that register back. The number of 0s returned starting from D4 for memory space and D2 for I/O space toward the high-order bits reveals the amount of address space desired. Tables 25 and 26 list the pos- sible returned values and their corresponding size for both memory and I/O, respectively. Included in the tables are the nvRAM/EPROM boot values which correspond to a given assigned size. A register returning all 0s indicates the region is disabled. Assigning the Base Address After a base address has been sized, the BIOS can physically locate it in memory (or I/O) space. The base address value must be on a natural binary boundary for the required size. For example, if the first base address register returns FFFFFF81h indicating an I/O space (D0=1) of size 80h. This means that the 5920’s internal registers can be selected for I/O addresses between 00000300h through 0000037Fh, in this example. (example 300h, 380h etc.; 338h, 340h would not be allowable). Register Name: Base Address Address Offset: 10h, 14h, 18h, 1Ch, 20h Power-up value: FFFFFF81h for offset 10h; 00000000h for all others Boot-load: External nvRAM offset 050h, 54h, 58h, 5Ch, 60h (BADR0-4) Attribute: high bits Read/Write; low bits Read Only Size: 32 bits |
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