CS5320 datasheet(83/160 Pages) AMCC

83 / 160 page

S5320 – PCI Match Maker: Initialization

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

Data Sheet

NON-VOLATILE MEMORY INTERFACE

The nv memory, can be accessed through the PCI

interface or the Add-On interface. Accesses to the nv

memory from the PCI interface are through the Reset

Control Register (RCR). Accesses to the nv memory

from the Add-On interface are through the Add-On

Reset Control Register (ARCR).

Some nv memories can contain Expansion ROM BIOS

code for use by the host CPU. During initialization, the

Expansion BIOS is located within system memory. The

starting location of the nv memory is stored in the

Expansion ROM Base Address Register in the S5320

PCI Configuration Registers. A PCI read from this

region results in the S5320 performing four consecu-

tive byte-wide access to the nv memory device, thus

assembling a complete DWORD. Writes to the nv

memory are not allowed through the expansion ROM

base address region. Any attempt to do so will result in

data being accepted by the S5320, but simply

discarded.

In the RCR and ARCR registers, bits D31:29 are com-

mand/status bits and bits D23:16 are address/data

bits. These operation registers occupy the same offset

(3Ch-3Fh) on their respective interfaces (Add-On or

PCI). The sequence used to access the nv memory is

the same in either case.

nvRAM READ/WRITE DESCRIPTION

There are four different mechanisms to access the

external nvRAM:

1. During boot-up (RST# deasserted), the S5320

will automatically read out the nvRAM addresses

40h - 7Fh.

2. Via the PCI Configuration Expansion ROM Base

Address Register (EXROM). This is READ-ONLY.

3. Via the PCI Reset Control Register (RCR). This is

READ/WRITE.

4. Via the Add-On Reset Control Register (ARCR).

This is READ/WRITE.

The boot-up sequence is a built-in function, and is

affected by the contents of the nvRAM. The Expansion

ROM Base Address Register is used if expansion

BIOS is stored in the external nvRAM. This register

can be enabled for a 2K memory size, and is mapped

to access the contents of the nvRAM. When a read is

performed to an address in the range of the EXROM

base address, a read sequence is started to the

nvRAM. As this sequence is extremely slow, the PCI

will be greeted with a Retry. Mean-while, the nvRAM

interface circuitry will be performing four sequential

byte accesses to the nvRAM at the offset indicated by

the PCI address. For example, if the EXROM Base

Address is programmed with 100000h, and the PCI

performs a read to address 100040h, this will initiate a

read from address 40h of the nvRAM. Once addresses

40h, 41h, 42h and 43h have been read and stored in

the nvRAM interface, the S5320 is ready to provide

the data to the original PCI device requesting the data.

Once the original master comes back to read the data

(which it should, as it received a Retry to its initial

read), it will get a TRDY# along with the 4 bytes of

data that were read from the nvRAM. If the master

comes back to retry the read, but the nvRAM interface

is not finished with its accesses, the master will again

be greeted with a Retry. If a master attempts to read

from a different EXROM address, it will also be

greeted with a Retry. Only a read with the original

address (in our example, a read to address 100040h)

will allow the transaction to complete. As a result, if the

original master never comes back to Retry the read,

the EXROM interface will be hung. Only other EXROM

accesses will be hung, as the nvRAM interface will still

be operational via the PCI’s RCR and the Add-On’s

ARCR.

Accesses to the nvRAM via the PCI’s Reset Control

grammer. There are 12 bits of this register that perform

both reads and writes. Bits 23-16 to provide Address/

Data information, bits 31-29 are used to provide con-

trol information, and bit 28 indicates whether the

nvRAM access was successful or not. The control bits

31-29 are assigned as follows (where W/R indicates

the type of PCI access to the RCR):

These control bits are used along with the Address/

Data bits 23-16 to configure the type of nvRAM opera-

tion (read or write), the address being accessed, and a

place to store the write data or the data read from the

nvRAM. One can interface with this register in either

byte-wide or word-wide fashion. For a word-wide

access, the command (bits 31-29) and Address/Data

(bits 23-16) are written to the RCR with one PCI write.

For a byte-wide access, the command (bits 31-29) is

written first, followed by the Address/Data (bits 23-16).

This takes two PCI transfers.

D31

D30

D29

W/R

nvRAM Interface Function

Inactive

Load low address byte

Load high address byte

Begin write

Begin read

Ready

Busy

CS5320 数据表(PDF) 83 Page - Applied Micro Circuits Corporation

CS5320 数据表(HTML) 83 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载