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CS5320 数据表(PDF) 47 Page - Applied Micro Circuits Corporation |
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CS5320 数据表(HTML) 47 Page - Applied Micro Circuits Corporation |
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47 / 160 page  S5320 – PCI Match Maker: PCI Configuration Registers Revision 5.03 – June 14, 2006 AMCC Confidential and Proprietary DS1656 47 Data Sheet Figure 17. Base Address Register - I/O Bit Description 31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return a 1 after being written as 1 are usable for this purpose. Except for Base Address 0, these bits are individually enabled by the contents sourced from the external nvRAM. 1 Reserved. This bit should be 0. (Note: disabled Base Address Registers will return all 0s for the entire register location, bits 31 through 0). 0 Space Indicator = 1. When 1, this bit identifies a base address region as an I/O space and the remaining bits in the base address register have the definition as shown in Figure 17. Base Address I/O Space Indicator (RO) Reserved (RO) 0 1 2 31 1 0 Programmable (R/W) Bit Value |
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