CS5320 datasheet(52/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Configuration Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Expansion ROM Base Address Register (XROM)

The Expansion ROM Base Address Register provides

a mechanism for assigning a space within physical

memory for a BIOS expansion ROM. Access from the

PCI bus to the memory space defined by this register

will cause one or more accesses to the S5320 external

nvRAM interface. Since PCI bus accesses to the ROM

may be 32 bits wide, repeated read operations to the

ROM are generated, and the wider data is assembled

internal to the S5320 controller. The data is then trans-

ferred to the PCI bus by the S5320. Only memory read

cycles should be performed to this location.

Figure 20. Expansion ROM Base Address Register

Expansion ROM Base Address

Address Offset:

30h

Power-up value:

00000000h

Boot-load:

External nvRAM offset 70h

Attribute:

bits 31:11, bit 0 Read/Write; bits 10:1

Read Only

Size:

32 bits

Bit

Description

31:11

Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space.

Only bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled

by the contents sourced from the external boot memory (nvRAM). The desired size for the ROM memory is

determined by writing all ones to this register and then reading back the contents. The number of bits returned

as zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This

controller limits the expansion ROM area to 2K bytes (due to the serial nvRAM’s limit of 11 bits of address). The

allowable returned values after all ones are written to this register are shown in Table 27.

10:1

Reserved. All zeros.

Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this

bit is set, the decoder is enabled. When this bit is cleared, the decoder is disabled. It is required the PCI com-

mand register (PCICMD) also have the memory decode bit enabled for this bit to have any effect. In addition,

the corresponding bit must be set in the external nvRAM (see page 80, Table 38). If not set, the PCI host cannot

enable/disable this Address Decode bit.

Address Decode

Enable (RW)

0 = Disabled

1 = Enabled

Reserved (RO)

Programmable (R/W)

Bit

Value

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