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CS5320 数据表(PDF) 6 Page - Applied Micro Circuits Corporation

部件名 CS5320
功能描述  PCI Match Maker, 3.3V
PDF  160 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

CS5320 数据表(HTML) 6 Page - Applied Micro Circuits Corporation

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S5320 – PCI Match Maker
6
DS1656
AMCC Confidential and Proprietary
Revision 5.03 – June 14, 2006
Data Sheet
TABLE OF CONTENTS
Add-On Incoming Mailbox Register (AIMB) ..................................................................................................... 70
Add-On Outgoing Mailbox Register (AOMB) ................................................................................................... 70
Add-On Pass-Thru Address Register (APTA) ................................................................................................. 70
Add-On Pass-Thru Data Register (APTD) ....................................................................................................... 70
Add-On Mailbox Empty/full Status Register (AMBEF) ..................................................................................... 71
Add-On Interrupt Control/status Register (AINT) ............................................................................................. 73
Add-On Reset Control Register (ARCR) ......................................................................................................... 75
Add-On Pass-thru Configuration Register (APTCR) ....................................................................................... 77
INITIALIZATION .................................................................................................................................................... 79
PCI RESET ............................................................................................................................................................ 79
LOADING THE SERIAL NV MEMORY ................................................................................................................. 79
NON-VOLATILE MEMORY INTERFACE ............................................................................................................. 83
NVRAM READ/WRITE DESCRIPTION ................................................................................................................. 83
PCI BUS CONFIGURATION CYCLES .................................................................................................................. 86
EXPANSION BIOS ROMS .................................................................................................................................... 87
PCI BUS INTERFACE ........................................................................................................................................... 91
PCI BUS TRANSACTIONS ................................................................................................................................... 91
PCI BURST TRANSFERS ..................................................................................................................................... 92
PCI READ TRANSFERS ....................................................................................................................................... 93
PCI WRITE TRANSFERS ..................................................................................................................................... 93
Target-Initiated Termination ............................................................................................................................ 94
Target Disconnects .......................................................................................................................................... 94
Target Requested Retries ............................................................................................................................... 94
Target Aborts ................................................................................................................................................... 95
Target Latency ................................................................................................................................................. 95
Target Locking ................................................................................................................................................. 95
PCI Bus Access Latency Components ............................................................................................................ 95
PCI BUS INTERRUPTS ........................................................................................................................................ 97
PCI BUS PARITY ERRORS .................................................................................................................................. 97
MAILBOX OVERVIEW ........................................................................................................................................ 100
FUNCTIONAL DESCRIPTION ............................................................................................................................ 100
Mailbox Empty/Full Conditions ...................................................................................................................... 101
Mailbox Interrupts .......................................................................................................................................... 101
Add-On Outgoing Mailbox, Byte 3 Access .................................................................................................... 102
BUS INTERFACE ................................................................................................................................................ 102
PCI Bus Interface .......................................................................................................................................... 102
Add-On Bus Interface .................................................................................................................................... 102
8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 103
CONFIGURATION ............................................................................................................................................... 103
Mailbox Status ............................................................................................................................................... 103
Writing the PCI Outgoing Mailbox: ................................................................................................................ 104



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