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CS5320 数据表(PDF) 94 Page - Applied Micro Circuits Corporation |
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CS5320 数据表(HTML) 94 Page - Applied Micro Circuits Corporation |
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94 / 160 page ![]() S5320 – PCI Match Maker: PCI Bus Protocol 94 DS1656 AMCC Confidential and Proprietary Revision 5.03 – June 14, 2006 Data Sheet Figure 45. Burst PCI Bus Read Attempt to S5320 Reg- isters or Expansion ROM Figure 46. Burst PCI Bus Write of S5320 Registers Target-Initiated Termination There are situations where the target may end a trans- fer prematurely. This is called “target-initiated termination.” Target termination falls into three catego- ries: disconnect, retry, and target abort. Only the disconnect termination completes a data transfer. Target Disconnects There are many situations where a target may discon- nect. Slow responding targets may disconnect to permit more efficient (faster) devices to be accessed while they prepare for the next data phase. Or a target may disconnect if it recognizes that the next data phase in a burst transfer is out of its address range. A target disconnects by asserting STOP#, TRDY#, and DEVSEL# as shown in Figures 47 and 48. The initiator in Figure 47 responds to the disconnect condition by deasserting FRAME# on the following clock but does not complete the data transfer until IRDY# is asserted. The timing diagram in Figure 48 also applies to the S5320. The S5320 performs a target disconnect if a burst access is attempted to any of its PCI Operation/Con- figuration Registers, or to the Expansion ROM. Target Requested Retries The S5320 initiates a retry for Pass-Thru writes when the Write FIFO is full, and for Pass-Thru reads when the Add-On cannot supply data within 16 PCI clocks from the assertion of FRAME# (for the first data phase of a burst). A retry is requested by a target by assert- ing both STOP# and DEVSEL# while TRDY# is deasserted. Figure 49 shows the behavior of the S5320 when performing a target-initiated retry. Figure 47. Target Disconnect Example 1 FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# 1 2 3 4 5 PCLK Address Data Bus Cmd Byte Enables (I) (T) (I) Driven by Initiator (T) Driven by Target FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# 1 2 3 4 5 PCLK Address Data 1 Bus Cmd BE 1 (I) (T) (I) Driven by Initiator (T) Driven by Target Data 2 BE 2 (I) (I) (I) (T) (T) Data Transfered No Data Transfered FRAME# IRDY# TRDY# DEVSEL# STOP# 1 2 3 4 5 PCLK (I) (T) (I) Driven by Initiator (T) Driven by Target (I) (T) (T) Data Transfered Target Disconnect Identified |
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