CS5320 datasheet(97/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Bus Protocol

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

Data Sheet

PCI BUS INTERRUPTS

The S5320 controller is able to generate PCI bus inter-

rupts by asserting the PCI bus interrupt signal (INTA#).

INTA# is a multi-sourced, wire-ORed signal on the PCI

bus and is driven by an open drain output on the

S5320. The assertion and deassertion of INTA# have

no fixed timing relationship with respect to the PCI bus

clock. Once the S5320 asserts INTA#, it remains

asserted until the interrupt source is cleared by a write

to the Interrupt Control/Status Register (INTCSR). In

the case of the external Add-On Interrupt, INTA# will

remain set as long as the ADDINT# pin is driven low

by an Add-On device(s). The source(s) driving ADD-

INT# must deassert this input before the PCI interrupt

(INTA#) is driven to the false state. It is the responsibil-

ity host software to clear the Add-On interrupt source

before exiting its interrupt handler routine.

PCI BUS PARITY ERRORS

The PCI specification defines two error-reporting sig-

nals, PERR# and SERR#. These signals indicate a

parity error condition on the signals AD[31:0], C/

BE[3:0]#, and PAR. The validity of the PAR signal is

delayed one clock period from its corresponding

AD[31:0] and C/BE[3:0]# signals. Even parity is sup-

ported by PCI: when the total number of ones in the

group of signals AD[31:0] and C/BE[3:0]# is equal to

an even number the parity bit will be deasserted. If an

odd number of ones is seen, the parity bit will be

asserted.

PERR# is the error-reporting mechanism for parity

errors that occur during the data phase for all but PCI

Special Cycle commands. SERR# is the error-report-

ing mechanism for parity errors that occur during the

address phase.

The timing diagram in Figure 53 shows the timing rela-

tionships between the signals AD[31:0], C/BE[3:0]#,

PAR, PERR# and SERR#.

The S5320 asserts SERR# if it detects odd parity dur-

ing an address phase, if enabled. The SERR# enable

bit is bit 8 in the S5320 PCI Command Register

(PCICMD). The odd parity error condition involves the

state of signals AD[31:0] and C/BE[3:0]# when

FRAME# is first asserted and the PAR signal during

the following clock. If an error is detected, the S5320

asserts SERR# on the following (after PAR valid)

clock. Since many targets may observe an error on an

address phase, the SERR# signal is an open-drain

multi-sourced, wire-ORed signal on the PCI bus. The

S5320 drives SERR# low for one clock period when

an address phase error is detected. Once an SERR#

error is detected by the S5320, the PCI Status register

bit 14, System Error, is set and remains set until

cleared through software or a hardware reset.

The PERR# signal is similar to the SERR# with two

differences: it reports errors for the data phase and is

only asserted by the device receiving the data. The

S5320 drives this signal (removed from tri-state) when

it is the selected target for write transactions. The par-

ity error conditions are only reflected by the PERR#

pin if the Parity Error Enable bit (bit 6) of the PCI Com-

mand Register is set. Upon the detection of a data

parity error, the Detected Parity Error bit (bit 15) of the

PCI Status Register is set (PCISTS). Unlike the

PERR# signal pin, this Status bit is set regardless of

the state of the PCI Command Register's Parity Error

Enable bit.

The assertion of PERR# occurs two clock periods fol-

lowing the data transfer. This two-clock delay occurs

because the PAR signal does not become valid until

the clock following the transfer, and an additional clock

is provided to generate and assert PERR# once an

error is detected. PERR# is only asserted for one

clock cycle for each error sensed. The S5320 only

qualifies the parity error detection during the actual

data transfer portion of a data phase (when both

IRDY# and TRDY# are asserted).

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