CS5320 datasheet(46/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Configuration Registers

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Figure 16. Base Address Register - Memory

Bit

Description

31:4

Base Address Location. These bits locate the decoded region in memory space. Only bits which return a 1 after

being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually

enabled by the contents sourced from the external boot memory.

Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cacheable regions

can only be located within the region altered through PCI bus memory writes. This bit, when set, also implies

that all read operations will return the data associated for all bytes regardless of the Byte Enables. Memory

space which cannot support this behavior should leave this bit in the zero state. this bit is set by the reset pin

and later initialized by the external boot memory option. Base Address Register 0 always has this bit set to 0.

This bit is read only from the PCI interface. This bit has no implementation in the S5320 other than providing it

during a configuration read cycle.

2:1

Memory Type. These bits define whether the memory space is 32 or 64 bits wide and if the space location is

restricted to be within the first megabyte of memory space. The encoding is as follows:

Bits

Description

Region is 32-bits wide and can be located anywhere in 32-bit memory space.

Region is 32 bits wide and must be mapped below the first Mbytes of memory space.

Region is 64 bits wide and can be mapped anywhere within 64-bit memory space. (Not supported

by this device.)

Reserved.

Note: The 64-bit memory space is not supported by this device. Bit 2 is hardwired to 0. Options are restricted to

desired to memory space anywhere within 32-bit memory space or located in the first megabyte. For Base

Addresses 1 through 4, this bit is cleared by the reset pin and later initialized by the external boot memory

option.

Space Indicator = 0. When set to 0, this bit defines a base address region as memory space and the remaining

bits in the base address register are defined as shown in Figure 16.

Base Address

Memory Space

Indicator (RO)

Type (RO)

00 = Locate

Anywhere (32)

01 = Below 1 MB

10 = Locate Anywhere (64)

11 = Reserved

Prefetchable (RO)

Programmable (RO)

Bit

Value

D31

D30

Add-On Bus Width

Region Disable

8 bits

16 bits

32 bits

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