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ADV7342 数据表(PDF) 39 Page - Analog Devices

部件名 ADV7342
功能描述  Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7342 数据表(HTML) 39 Page - Analog Devices

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ADV7342/ADV7343
Rev. 0 | Page 39 of 88
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
Reserved.
0
0x00
0
Disabled.
SD Noninterlaced Mode.
1
Enabled.
0
Disabled.
SD Double Buffering.
1
Enabled.
0
0
8-bit input.
0
1
16-bit input.
1
0
Reserved.
SD Input Format.
1
1
Reserved.
0
Disabled.
SD Digital Noise Reduction.
1
Enabled.
0
Disabled.
SD Gamma Correction Enable.
1
Enabled.
0
Gamma Correction Curve A.
0x88
SD Mode
Register 7
SD Gamma Correction Curve Select.
1
Gamma Correction Curve B.
0
0
Disabled.
0x00
0
1
−11 IRE.
1
0
−6 IRE.
SD Undershoot Limiter.
1
1
−1.5 IRE.
Reserved.
0
0 must be written to this bit.
0
Disabled.
SD Black Burst Output on DAC
Luma.
1
Enabled.
0
0
Disabled.
0
1
4 clock cycles.
1
0
8 clock cycles.
SD Chroma Delay.
1
1
Reserved.
0x89
SD Mode
Register 8
Reserved.
0
0
0 must be written to these bits.
1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.



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