ADV7342 datasheet(56/88 Pages) AD

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ADV7342/ADV7343

Rev. 0 | Page 56 of 88

DOUBLE BUFFERING

Subaddress 0x33, Bit 7 for ED/HD,

Subaddress 0x88, Bit 2 for SD

Double-buffered registers are updated once per field. Double

buffering improves overall performance, because modifications

to register settings are not made during active video, but take

effect prior to the start of the active video on the next field.

Double buffering can be activated on the following ED/HD

registers using Subaddress 0x33, Bit 7: ED/HD Gamma A and

Gamma B curves, and ED/HD CGMS registers.

Double buffering can be activated on the following SD registers

using Subaddress 0x88, Bit 2: SD Gamma A and Gamma B

curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD

closed captioning, and SD Macrovision Bits[5:0] (Subaddress

0xE0, Bits[5:0]).

PROGRAMMABLE DAC GAIN CONTROL

Subaddress 0x0A to Subaddress 0x0B

It is possible to adjust the DAC output signal gain up or down

from its absolute level. This is illustrated in Figure 69.

DAC 4 to DAC 6 are controlled by Register 0x0A.

DAC 1 to DAC 3 are controlled by Register 0x0B.

CASE B

700mV

300mV

NEGATIVE GAIN PROGRAMMED IN

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0A, 0x0B

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0A, 0x0B

700mV

300mV

Figure 69. Programmable DAC Gain—Positive and Negative Gain

In Case A of Figure 69, the video output signal is gained. The

absolute level of the sync tip and blanking level both increase

with respect to the reference video output signal. The overall

gain of the signal is increased from the reference signal.

In Case B of Figure 69, the video output signal is reduced. The

absolute level of the sync tip and blanking level both decrease

with respect to the reference video output signal. The overall

gain of the signal is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal

output from the DACs. For example, if the output current of the

DAC is 4.33 mA, the DAC gain control feature can change this

output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

The reset value of the control registers is 0x00, that is, nominal

DAC current is output. Table 46 is an example of how the

output current of the DACs varies for a nominal 4.33 mA

output current.

Table 46. DAC Gain Control

Reg. 0x0A or

Reg.0x0B

DAC

Current (mA)

% Gain

Note

0100 0000 (0x40)

4.658

7.5000%

0011 1111 (0x3F)

4.653

7.3820%

0011 1110 (0x3E)

4.648

7.3640%

...

0000 0010 (0x02)

4.43

0.0360%

0000 0001 (0x01)

4.38

0.0180%

0000 0000 (0x00)

4.33

0.0000%

Reset value,

nominal

1111 1111 (0xFF)

4.25

−0.0180%

1111 1110 (0xFE)

4.23

−0.0360%

...

1100 0010 (0xC2)

4.018

−7.3640%

1100 0001 (0xC1)

4.013

−7.3820%

1100 0000 (0xC0)

4.008

−7.5000%

GAMMA CORRECTION

Subaddress 0x44 to Subaddress 0x57 for ED/HD,

Subaddress 0xA6 to Subaddress 0xB9 for SD

Generally, gamma correction is applied to compensate for the

nonlinear relationship between signal input and output

brightness level (as perceived on a CRT). It can also be applied

wherever nonlinear processing is used.

Gamma correction uses the function

SignalOUT

= (SignalIN)γ

where γ = is the gamma correction factor.

Gamma correction is available for SD and ED/HD video. For

both variations, there are 20, 8-bit registers. They are used to

program the Gamma Correction Curve A and Gamma

Correction Curve B.

ED/HD gamma correction is enabled using Subaddress 0x35,

Bit 5. ED/HD Gamma Correction Curve A is programmed at

Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma

Correction Curve B is programmed at Subaddress 0x4E to

Subaddress 0x57.

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