ADV7342 datasheet(8/88 Pages) AD

8 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 8 of 88

MPU PORT TIMING SPECIFICATIONS

VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.

All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.

Table 8.

Parameter

Conditions

Min

Typ

Max

Unit

MPU PORT, I2C MODE1

SCL Frequency

400

kHz

SCL High Pulse Width, t1

0.6

μs

SCL Low Pulse Width, t2

1.3

μs

Hold Time (Start Condition), t3

0.6

μs

Setup Time (Start Condition), t4

0.6

μs

Data Setup Time, t5

100

SDA, SCL Rise Time, t6

300

SDA, SCL Fall Time, t7

300

Setup Time (Stop Condition), t8

See Figure 19

0.6

μs

MPU PORT, SPI MODE1

SCLK Frequency

MHz

SPI_SS to SCLK Setup Time, t1

SCLK High Pulse Width, t2

SCLK Low Pulse Width, t3

Data Access Time after SCLK Falling Edge, t4

Data Setup Time prior to SCLK Rising Edge, t5

Data Hold Time after SCLK Rising Edge, t6

SPI_SS to SCLK Hold Time, t7

SPI_SS to MISO High Impedance, t8

See Figure 20

1 Guaranteed by characterization.

POWER SPECIFICATIONS

VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.

Table 9.

Parameter

Conditions

Min

Typ

Max

Unit

NORMAL POWER MODE1, 2

IDD3

SD only (16× oversampling)

ED only (8× oversampling)4

HD only (4× oversampling)4

SD (16× oversampling) and ED (8× oversampling)

SD (16× oversampling) and HD (4× oversampling)

122

IDD_IO

IAA

3 DACs enabled (ED/HD only)

124

6 DACs enabled (SD only and simultaneous modes )

140

IPLL

SD only, ED only or HD only modes

Simultaneous modes

SLEEP MODE

IDD

μA

IAA

0.3

μA

IDD_IO

0.2

μA

IPLL

0.1

μA

1 RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).

2 75% color bar test pattern applied to pixel data pins.

3 IDD is the continuous current required to drive the digital core.

4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.

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