ADV7342 datasheet(63/88 Pages) AD

63 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 63 of 88

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input

pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see

Table 49). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52).

Table 49. Timing Synchronization Signal Input Options

Signal

Condition

SD HSYNC In

S_HSYNC

SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).1

SD VSYNC/FIELD In

S_VSYNC

SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).1

ED/HD HSYNC In

P_HSYNC

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

ED/HD VSYNC/FIELD In

P_VSYNC

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

ED/HD BLANK In

P_BLANK

1 SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 50. Timing Synchronization Signal Output Options

Signal

Condition

SD HSYNC Out

S_HSYNC

SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).1

SD VSYNC/FIELD Out

S_VSYNC

SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).1

ED/HD HSYNC Out

S_HSYNC

ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).

ED/HD VSYNC/FIELD Out

S_VSYNC

ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).

1 ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

Table 51. S_HSYNC Output Control1

ED/HD Input Sync

Format (0x30, Bit 2)

ED/HD HSYNC

Control

(0x34, Bit 1)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

Signal on S_HSYNC Pin

Duration

Tristate.

–

Pipelined SD HSYNC.

See

Appendix 5—

SD Timing.

Pipelined ED/HD HSYNC.

As per HSYNC timing.

Pipelined ED/HD HSYNC based on

AV Code H bit.

Same as line blanking

interval.

Pipelined ED/HD HSYNC based on

horizontal counter.

Same as embedded

HSYNC.

1 In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.

Table 52. S_VSYNC Output Control1

ED/HD Input

Sync Format

(0x30, Bit 2)

ED/HD VSYNC

Control

(0x34, Bit 2)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

Video Standard

Signal on S_VSYNC Pin

Duration

Tristate.

–

Interlaced

Pipelined SD VSYNC

/Field.

See

Appendix

5—SD Timing.

Pipelined ED/HD VSYNC

or field signal.

As per VSYNC or

field signal timing.

All HD interlaced

standards

Pipelined field signal

based on AV Code F bit.

Field.

All ED/HD

progressive

standards

Pipelined VSYNC based

on AV Code V bit.

Vertical blanking

interval.

All ED/HD

standards

except 525p

Pipelined ED/HD VSYNC

based on vertical counter.

Aligned with

serration lines.

525p

Pipelined ED/HD VSYNC

based on vertical counter.

Vertical blanking

interval.

1 In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.

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