ADV7342 datasheet(7/88 Pages) AD

7 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 7 of 88

DIGITAL TIMING SPECIFICATIONS

VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.

All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.

Table 7.

Parameter

Conditions1

Min

Typ

Max

Unit

VIDEO DATA AND VIDEO CONTROL PORT2, 3

Data Setup Time, t114

2.1

ED/HD-SDR

2.3

ED/HD-DDR

2.3

ED (at 54 MHz)

1.7

Data Hold Time, t124

1.0

ED/HD-SDR

1.1

ED/HD-DDR

1.1

ED (at 54 MHz)

1.0

Control Setup Time, t114

2.1

ED/HD-SDR or ED/HD-DDR

2.3

ED (at 54 MHz)

1.7

Control Hold Time, t124

1.0

ED/HD-SDR or ED/HD-DDR

1.1

ED (at 54 MHz)

1.0

Digital Output Access Time, t134

ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)

Digital Output Hold Time, t144

4.0

ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)

3.5

PIPELINE DELAY5

SD1

CVBS/YC Outputs (2×)

SD oversampling disabled

clock cycles

CVBS/YC Outputs (16×)

SD oversampling enabled

clock cycles

Component Outputs (2×)

SD oversampling disabled

clock cycles

Component Outputs (16×)

SD oversampling enabled

clock cycles

ED1

Component Outputs (1×)

ED oversampling disabled

clock cycles

Component Outputs (8×)

ED oversampling enabled

clock cycles

HD1

Component Outputs (1×)

HD oversampling disabled

clock cycles

Component Outputs (4×)

HD oversampling enabled

clock cycles

1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

2 Video data: C[7:0], Y[7:0], and S[7:0].

3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.

4 Guaranteed by characterization.

5 Guaranteed by design.

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