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ADV7342 数据表(PDF) 28 Page - Analog Devices

部件名 ADV7342
功能描述  Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7342 数据表(HTML) 28 Page - Analog Devices

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ADV7342/ADV7343
Rev. 0 | Page 28 of 88
Table 15. Register 0x01 to Register 0x09
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
Reserved.
0
0x00
0
0
Chroma clocked in on rising clock edge;
luma clocked in on falling clock edge.
0
1
Reserved.
1
0
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED1 and
HD DDR modes.
1
1
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge.
Reserved.
0
0
0
0
SD input only.
0
0
1
ED/HD-SDR input only.
0
1
0
ED/HD-DDR input only.
0
1
1
SD and ED/HD-SDR.
1
0
0
SD and ED/HD-DDR.
1
0
1
Reserved.
1
1
0
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
1
1
1
ED only (at 54 MHz).
0
0x01
Mode Select
Register
Y/C/S Bus Swap.
1
Allows data to be applied to data ports in
various configurations (SD feature only).
Reserved.
0
0
0 must be written to these bits.
0x20
0
Disabled.
Test Pattern Black Bar.2
1
Enabled.
0
Disable manual CSC matrix adjust.
Manual CSC Matrix Adjust.
1
Enable manual CSC matrix adjust.
0
No sync.
Sync on RGB.
1
Sync on all RGB outputs.
0
RGB component outputs.
RGB/YPrPb Output Select.
1
YPrPb component outputs.
0
No sync output.
SD Sync Output Enable.
1
Output SD syncs on S_HSYNC and
S_VSYNC pins.
0
No sync output.
0x02
Mode
Register 0
ED/HD Sync Output Enable.
1
Output ED/HD syncs on S_HSYNC and
S_VSYNC pins.
0x03
ED/HD CSC
Matrix 0
x
x
LSBs for GY.
0x03
x
x
LSBs for RV.
0xF0
x
x
LSBs for BU.
x
x
LSBs for GV.
0x04
ED/HD CSC
Matrix 1
x
x
LSBs for GU.
0x05
ED/HD CSC
Matrix 2
x
x
x
x
x
x
x
x
Bits[9:2 ] for GY.
0x4E
0x06
ED/HD CSC
Matrix 3
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
0x07
ED/HD CSC
Matrix 4
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
0x08
ED/HD CSC
Matrix 5
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
0x09
ED/HD CSC
Matrix 6
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
1 ED = enhanced definition = 525p and 625p.
2 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).



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