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ADV7342 数据表(PDF) 33 Page - Analog Devices

部件名 ADV7342
功能描述  Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
PDF  88 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7342 数据表(HTML) 33 Page - Analog Devices

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ADV7342/ADV7343
Rev. 0 | Page 33 of 88
Table 20. Register 0x34 to Register 0x35
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0
Internal ED/HD timing counters enabled.
0x48
ED/HD Timing Reset.
1
Resets the internal ED/HD timing counters.
0
ED/HD HSYNC Control.1
1
HSYNC output control (refer to
Table 51).
0
ED/HD VSYNC Control.1
1
VSYNC output control (refer to
Table 52).
0
P_BLANK active high.
ED/HD Blank Polarity.
1
P_BLANK active low.
0
Macrovision disabled.
ED Macrovision Enable.
1
Macrovision enabled.
Reserved.
0
0 must be written to this bit.
0
0 = field input.
ED/HD VSYNC/Field Input.
1
1 = VSYNC input.
0
Update field/line counter.
0x34
ED/HD Mode
Register 5
Horizontal/Vertical
Counters.2
1
Field/line counter free running.
Reserved.
0
0x00
0
Disabled.
ED/HD RGB Input Enable.
1
Enabled.
0
Disabled.
ED/HD Sync on PrPb.
1
Enabled.
0
DAC 2 = Pb, DAC 3 = Pr.
ED/HD Color DAC Swap.
1
DAC 2 = Pr, DAC 3 = Pb.
0
Gamma Correction Curve A.
ED/HD Gamma
Correction Curve Select.
1
Gamma Correction Curve B.
0
Disabled.
ED/HD Gamma
Correction Enable.
1
Enabled.
0
Mode A.
ED/HD Adaptive
Filter Mode.
1
Mode B.
0
Disabled.
0x35
ED/HD Mode
Register 6
ED/HD Adaptive
Filter Enable
1
Enabled.
1 Used in conjunction with ED/HD sync in Subaddress 0x02, Bit 7, set to 1.
2 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.



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