ADV7342 datasheet(67/88 Pages) AD

67 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 67 of 88

Power Supply Decoupling

It is recommended that each power supply pin be decoupled

with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD,

VDD_IO, and both VDD pins should be individually decoupled to

ground. The decoupling capacitors should be placed as close as

possible to the ADV7342/ADV7343 with the capacitor leads

kept as short as possible to minimize lead inductance.

A 1 μF tantalum capacitor is recommended across the VAA

supply in addition to the 10 nF and 0.1 μF ceramic capacitors.

Power Supply Sequencing

The ADV7342/ADV7343 are robust to all power supply

sequencing combinations. Any particular sequence can be used.

Digital Signal Interconnect

The digital signal traces should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal traces should not overlay the VAA or PVDD power planes.

Due to the high clock rates used, avoid long clock traces to the

ADV7342/ADV7343 to minimize noise pickup.

Any pull-up termination resistors for the digital inputs should

be connected to the VDD power supply.

Any unused digital inputs should be tied to ground.

Analog Signal Interconnect

DAC output traces should be treated as transmission lines with

appropriate measures taken to ensure optimal performance (for

example, impedance matched traces). The DAC output traces

should be kept as short as possible. The termination resistors on

the DAC output traces should be placed as close as possible to

and on the same side of the PCB as the ADV7342/ADV7343.

To avoid crosstalk between the DAC outputs, it is recom-

mended that as much space as possible be left between the

traces connected to the DAC output pins. Adding ground traces

between the DAC output traces is also recommended.

ADV7342 数据表(PDF) 67 Page - Analog Devices