ADV7342 datasheet(64/88 Pages) AD

64 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 64 of 88

LOW POWER MODE

Subaddress 0x0D, Bits[2:0]

For power sensitive applications, the ADV7342/ADV7343

support an Analog Devices, Inc. proprietary low power mode of

operation on DAC 1, DAC 2, and DAC 3. To utilize this low

power mode, these DACs must be operating in full-drive mode

(RSET = 510 Ω, RL = 37.5 Ω). Low power mode is not available in

low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode

can be independently enabled or disabled on DAC 1, DAC 2, and

DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is

disabled by default on each DAC.

In low power mode, DAC current consumption is content

dependent. On a typical video stream, it can be reduced by as

much as 40%. For applications requiring the highest possible video

performance, low power mode should be disabled.

CABLE DETECTION

Subaddress 0x10

The ADV7342/ADV7343 include an Analog Devices, Inc.

proprietary cable detection feature.

The cable detection feature is available on DAC 1 and DAC 2,

while operating in full-drive mode (RSET1 = 510 Ω, RL1 = 37.5 Ω,

assuming a connected cable). The feature is not available in low

drive mode (RSET = 4.12 kΩ, RL = 300 Ω). For a DAC to be

monitored, the DAC must be powered up in Subaddress 0x00.

The cable detection feature can be used with all SD, ED, and

HD video standards. It is available for all output configurations,

that is, CVBS, YC, YPrPb, and RGB output configurations.

For CVBS/YC output configurations, both DAC 1 and DAC 2

are monitored, that is, the CVBS and YC luma outputs are

monitored. For YPrPb and RGB output configurations, only

DAC 1 is monitored, that is, the luma or green output is

monitored.

Once per frame, the ADV7342/ADV7343 monitor DAC 1

and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,

respectively. If a cable is detected on one of the DACs, the

relevant bit is set to 0. If not, the bit is set to 1.

DAC AUTO POWER-DOWN

Subaddress 0x10, Bit 4

For power sensitive applications, a DAC auto power-down

feature can be enabled using Subaddress 0x10, Bit 4. This feature

is only available when the cable detection feature is enabled.

With this feature enabled, the cable detection circuitry monitors

DAC 1 and/or DAC 2 once per frame. If they are unconnected,

some or all of the DACs automatically power down. Which

DAC or DACs are powered down depends on the selected

output configuration.

For CVBS/YC output configurations, if DAC 1 is unconnected,

only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and

DAC 3 power down.

For YPrPb and RGB output configurations, if DAC 1 is

unconnected, all three DACs power down. DAC 2 is not

monitored for YPrPb and RGB output configurations.

Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable

is detected, the appropriate DAC or DACs remain powered up

for the duration of the frame. If no cable is detected, the appropriate

DAC or DACs power down until the next frame, when the process

is repeated.

PIXEL AND CONTROL PORT READBACK

Subaddress 0x12 to Subaddress 0x14, Subaddress 0x16

The ADV7342/ADV7343 support the readback of most digital

inputs via the I2C/SPI MPU port. This feature is useful for

board level connectivity testing with upstream devices.

The pixel port (S[7:0], Y[7:0], and C[7:0]), the control port

(S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC and P_BLANK),

and the SFL/MISO pin are available for readback via the MPU

port. The readback registers are located at Subaddress 0x12 to

Subaddress 0x14 and Subaddress 0x16.

When using this feature, a clock signal should be applied to the

CLKIN_A pin to register the levels applied to the input pins.

RESET MECHANISM

Subaddress 0x17, Bit 1

The ADV7342/ADV7343 have a software reset accessible via

the I2C/SPI MPU port. A software reset is activated by writing

a 1 to Subaddress 0x17, Bit 1. This resets all registers to their

default values. This bit is self-clearing, that is, after a 1 has been

written to the bit, the bit automatically returns to 0.

When operating in SPI mode, a software reset does not cause

the device to revert to I2C mode. For this to occur, the

ADV7342/ADV7343 need to be powered down.

The ADV7342/ADV7343 include a power-on reset (POR)

circuit to ensure correct operation after power-up.

ADV7342 数据表(PDF) 64 Page - Analog Devices

ADV7342 数据表(HTML) 64 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载