ADV7342 datasheet(18/88 Pages) AD

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ADV7342/ADV7343

Rev. 0 | Page 18 of 88

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RSET1

VREF

COMP1

DAC 3

DAC 2

DAC 1

SFL/MISO

VAA

AGND

DAC 4

DAC 6

RSET2

COMP2

PVDD

EXT_LF1

DAC 5

TEST0

TEST1

VDD_IO

VDD

TEST2

TEST3

DGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PIN 1

ADV7342/ADV7343

TOP VIEW

(Not to Scale)

Figure 21. Pin Configuration

Table 13. Pin Function Descriptions

Pin No.

Mnemonic

Input/

Output

Description

13, 12,

9 to 4

Y7 to Y0

8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.

29 to 25,

18 to 16

C7 to C0

8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.

62 to 58,

55 to 53

S7 to S0

8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.

52, 51, 15,

14, 3, 2

TEST5 to

TEST0

Unused. These pins should be connected to DGND.

CLKIN_A

Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz) or SD Only (27 MHz).

CLKIN_B

Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a

74.25 MHz reference clock for HD operation.

S_HSYNC

I/O

SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

horizontal synchronization signal. See the External Horizontal and Vertical Synchronization

Control section.

S_VSYNC

I/O

SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control

section.

P_HSYNC

ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical

Synchronization Control section.

P_VSYNC

ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization

Control section.

P_BLANK

ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.

SFL/MISO

I/O

Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is

used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.

RSET1

This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive

operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET1 to

AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be

connected from RSET1 to AGND.

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