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ADV7342 数据表(PDF) 32 Page - Analog Devices

部件名 ADV7342
功能描述  Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
PDF  88 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7342 数据表(HTML) 32 Page - Analog Devices

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ADV7342/ADV7343
Rev. 0 | Page 32 of 88
Table 19. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0
Pixel data valid off.
0x00
ED/HD Pixel Data Valid.
1
Pixel data valid on.
Reserved.
0
0
ED/HD test pattern off.
ED/HD Test Pattern Enable.
1
ED/HD test pattern on.
0
Hatch.
ED/HD Test Pattern Hatch/Field.
1
Field/frame.
0
Disabled.
ED/HD VBI Open.
1
Enabled.
0
0
Disabled.
0
1
−11 IRE
1
0
−6 IRE
ED/HD Undershoot Limiter.
1
1
−1.5 IRE
0
Disabled.
0x31
ED/HD Mode
Register 2
ED/HD Sharpness Filter.
1
Enabled.
0
0
0
0 clock cycles.
0x00
0
0
1
1 clock cycle.
0
1
0
2 clock cycles.
0
1
1
3 clock cycles.
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
1
0
0
4 clock cycles.
0
0
0
0 clock cycles.
0
0
1
1 clock cycle.
0
1
0
2 clock cycles.
0
1
1
3 clock cycles.
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
1
0
0
4 clock cycles.
0
Disabled.
ED/HD CGMS.
1
Enabled.
0
Disabled.
0x32
ED/HD Mode
Register 3
ED/HD CGMS CRC.
1
Enabled.
0
Cb after falling edge of HSYNC.
0x68
ED/HD Cr/Cb Sequence.
1
Cr after falling edge of HSYNC.
Reserved.
0
0
0 must be written to these bits.
0
Disabled.
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
1
Enabled.
Reserved.
0
0 must be written to this bit.
0
Disabled.
ED/HD Chroma SSAF.
1
Enabled.
0
4:4:4
ED/HD Chroma Input.
1
4:2:2
0
Disabled.
0x33
ED/HD Mode
Register 4
ED/HD Double Buffering.
1
Enabled.



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