CS43L21 datasheet(6/63 Pages) CIRRUS

6 / 63 page

DS723A1

CS43L21

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

Pin Name

Pin Description

LRCK

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SDA/CDIN

(MCLKDIV2)

Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the

control port interface in SPI Mode.

MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.

SCL/CCLK

(I²S/LJ)

Serial Control Port Clock (Input) - Serial clock for the serial control port.

Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-

mats for the DAC.

AD0/CS

(DEM)

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS

is the chip-select signal for SPI format.

De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.

VA_HP

Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.

FLYP

Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.

GND_HP

Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.

FLYN

Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.

VSS_HP

Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-

phone section.

CS43L21

SDA/CDIN (MCLKDIV2)

SCL/CCLK (I²S/LJ)

ADO/CS (DEM)

FLYP

GND_HP

FLYN

TSTO

VA_HP

LRCK

CS43L21 数据表(PDF) 6 Page - Cirrus Logic

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