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CS43L21 数据表(PDF) 29 Page - Cirrus Logic

部件名 CS43L21
功能描述  Low Power, Stereo Digital to Analog Converter
PDF  63 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS43L21 数据表(HTML) 29 Page - Cirrus Logic

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DS723A1
29
CS43L21
4.4.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.4.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect
QSM
HSM
SSM
DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
256, 384, 512, 768,
1024, 1536
128, 192, 256, 384,
512, 768
128, 192, 256, 384
Enabled
1024, 1536, 2048*,
3072*
512, 768, 1024*, 1536*
256, 384, 512*, 768*
128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1
0
1
MCLK
MCLKDIV2
÷ 128
00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2
00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 12. Master Mode Timing



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