CS43L21 datasheet(17/63 Pages) CIRRUS

部件名	CS43L21

功能描述	Low Power, Stereo Digital to Analog Converter

PDF	63 Pages

Scroll/Zoom	100%

制造商	CIRRUS [Cirrus Logic]

网页	http://www.cirrus.com

标志

17 / 63 page

DS723A1

CS43L21

10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are set-

tled.

11. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.

12. See “Master” on page 29

Master Mode (Note 12)

Output Sample Rate (LRCK)

All Speed Modes

-Hz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

LRCK Edge to SDIN MSB Rising Edge

td(MSB)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Parameters

Symbol

Min

Max

Units

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

ts(LK-SK)

Figure 4. Serial Audio Interface Slave Mode Timing

MCLK

128

-----------------

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

td(MSB)

Figure 5. Serial Audio Interface Master Mode Timing

CS43L21 数据表(PDF) 17 Page - Cirrus Logic

CS43L21 数据表(HTML) 17 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

数据表下载

链接网址

CS43L21 数据表(PDF) 17 Page - Cirrus Logic

CS43L21 数据表(HTML) 17 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

数据表 下载

链接网址

数据表下载