CS43L21 datasheet(16/63 Pages) CIRRUS

16 / 63 page

DS723A1

CS43L21

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Notes:

Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30

on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

Measurement Bandwidth is from Stopband to 3 Fs.

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL.)

Parameter (Note 8)

Min

Typ

Max

Unit

Frequency Response 10 Hz to 20 kHz

-0.01

+0.08

Passband

to -0.05 dB corner

to -3 dB corner

0.4780

0.4996

StopBand

0.5465

StopBand Attenuation (Note 9)

Group Delay

10.4/Fs

De-emphasis Error

Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+1.5/+0

+0.05/-0.25

-0.2/-0.4

Parameters

Symbol

Min

Max

Units

RESET pin Low Pulse Width

(Note 10)

MCLK Frequency

1.024

38.4

MHz

MCLK Duty Cycle

(Note 11)

Slave Mode

Input Sample Rate (LRCK)

Quarter-Speed Mode

Half-Speed Mode

Single-Speed Mode

Double-Speed Mode

12.5

100

kHz

LRCK Duty Cycle

SCLK Frequency

1/tP

-64•Fs

SCLK Duty Cycle

LRCK Setup Time Before SCLK Rising Edge

ts(LK-SK)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

CS43L21 数据表(PDF) 16 Page - Cirrus Logic

CS43L21 数据表(HTML) 16 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

数据表下载