CS43L21 datasheet(31/63 Pages) CIRRUS

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DS723A1

CS43L21

4.6

Initialization

The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 32. The CODEC en-

ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-

lators and control port registers are reset. The internal voltage reference, multi-bit DAC and switched-

capacitor low-pass filters are powered down.

The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-

cessible once RESET is high and the desired register settings can be loaded per the interface descriptions

in “Software Mode” on page 33. If a valid write sequence to the control port is not made within approximately

10 ms, the will enter Hardware Mode.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, FILT+ will begin pow-

ering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then

applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-

ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the

MCLK/LRCK frequency ratio and normal operation begins.

4.7

Recommended Power-Up Sequence

Hold RESET low until the power supplies are stable.

Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.

For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-

by”.

Load the desired register settings while keeping the PDN bit set to ‘1’b.

Start MCLK to the appropriate frequency, as discussed in Section 4.4.

Set the PDN bit to ‘0’b.

Apply LRCKSCLK and SDIN for normal operation to begin.

Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

LRCK

SCLK

MS B

LS B

MS B

LS B

L e ft C han ne l

R ig h t C h an n e l

SDIN

MSB

AOUTA / AINxA

AOUTB / AINxB

Figure 15. Left-Justified Format

LRCK

SCLK

MS B

LS B

MS B

LS B

Left C han ne l

R ig h t C han ne l

SDIN

AOUTA

AOUTB

Figure 16. Right-Justified Format (DAC only)

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